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1/51 key features knx ? interface uart host interface included power supplies: spi? host interface applications typical application circuit ? certified with knx ? tp1-256 application ? autonomous mac and individual physical address ? included protocol handling ? included power supply for bus powered applications with selectable bus current limitation ? extended frames with up to 254 byte payload ? analog mode (direct rx / tx interface) ? autonomous telegram trigger ? alarm telegram ? autonomous poll data transfer ? supports 9.6 k, 19.2 k, 115.2 k ? 9 bit mode for easy data stream interpretation ? optional crc (at 19.2kbd and 115.2 kbd) ? if not used 4 gpios are available ? 20v supply, up to 20ma ? 3.3v (70ma) / 5v (70ma) dc/dc converter ? sensors, actuators, routers, gateways, bus-powered or externally supplied ? security applications is a konnex association registered trademark. spi? is a motorola inc. trademark. general description the e981.03 combines the tp1-256 physical layer, the communication controller and two dc supply outputs for bus powered applications. the internal power man - agement assures knx conformance under all load con - ditions. the connection between the e981.03 and the host pro - cessor can be established by either uart or spi compat - ible interfaces, or in direct analog mode. ordering information ordering-no.: temp range package E98103A38B -25c to +85c qfn32l7 r tx r txl typical application circuit **1 d 1 busp c rec r tx crec rtxh rtxl busn extal xtal gnd rxd txd vio set_vcc e981.03 u a r t c a p p l i ca t i o n bus coupling module vcc r set tp1-256 + - u 1 c 33i c st c vcc c cvcc d sps l sps v33i vst sw vcc c cst c 20 v20 20v c vio q functional diagram **2 (5) setvcc e981.03 (2) reset (1) otemp clock system knx / eib interface uart host interface (12) busp (8) crec (11) rtxh (10) rtxl (9) busn (23) extal (24) xtal (27) gnd (26) rxd (25) txd (19) vio (31) miso / gpio (30) mosi / gpio (29) sck / gpi (28) scs / gpi spi host interface c v20 (3) i.c. (13) i.c. ic supply ic start-up 20v supply current limiter adc/dac internal logic (21) bs1 (20) bs0 (32) save (4) aout monitoring unit (22) int mode control (7) wk / gpi switched power supply c 33i c st c vcc c cvcc d sps l sps (6) v33i (15) vst (17) sw vcc c cst (14) v20 (16) i.c. r vcc (18) vcc v20 d 1 c rec r tx + - u 1 q tp1-256 + - minimal function of e981.03 **3 bus coupling module u ar t h o s t p ro ce sso r o p t i o n a l o p t o - co u p l e r application module q u 1 c cst c st r tx c rec c 33i c vcc c cvcc d sps l sps r vcc c vio d 1 d vio r set v vio = v vcc (50ma) setvcc=v io q v vio v vio o t e m p i n t b s 0 v i o v c c s w x t a l e x t a l b s 1 gnd scs sck miso mosi txd rxd e l a - 0 1 2 0 33 v 3 3 i a o u t i . c. r e s e t v20 c r e c w k vst i.c. e9 8 1 . 0 3 busn rtxl rtxh busp 16 15 14 13 12 11 10 9 25 26 27 28 29 30 31 32 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 2 3 4 5 6 7 8 s e t v c c gnd mosi txd e l a - 0 1 2 0 33 i.c. e981.03 rtxl 16 15 14 13 12 11 10 9 25 26 27 28 29 30 31 32 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 2 3 4 5 6 7 8 save ic1 r txl full normal mode application **4 bus coupling module o p t i o n a l o p t o - c o u p l e r o p t i o n a l o p t o - c o u p l e r v vio u ar t h o st p ro ce ss o r s pi o p t i o n o p t i o n a l o p t o - c o u p l e r gpio analog in gpio / resetn gpio o p t i o n a l o p t o co u p l e r gpio vcc= 3.3v vcc= 5v open= alarm v v20 =20v / 20ma v vcc v vio gpio o p t i o n a l o p t o - c o u p l e r u 1 c cst c st c rec c 33i c vcc c cvcc d sps l sps r vcc c vio d 1 d vio r set q v vcc = 3.3v (50ma) setvcc=gnd v vcc = 5v (30ma) setvcc=v vio o t e m p i n t b s 0 v i o v c c s w x t a l e x t a l b s 1 gnd scs sck miso mosi txd rxd e l a - 0 1 2 0 33 v 3 3 i a o u t i . c. r e s e t v20 c r e c w k vst i.c. e9 8 1 . 0 3 busn rtxl rtxh busp 16 15 14 13 12 11 10 9 25 26 27 28 29 30 31 32 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 2 3 4 5 6 7 8 s e t v c c gnd mosi txd e l a - 0 1 2 0 33 i.c. e981.03 rtxl 16 15 14 13 12 11 10 9 25 26 27 28 29 30 31 32 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 2 3 4 5 6 7 8 save ic1 c 20 o p t i o n a l i so l a t i o n a m p l i f i e r r txl r tx l elmos semiconductor ag data sheet qm-no.: 25ds0046e.03 knx / eib transceiver e981.03 elmos semiconductor ag reserves the right to change the detail specifcations as may be required to permit improvements in the design of its products. production data - jan 15, 2015
2/51 pin confguration top view note: not to scale, ep exposed die pad functional diagram txd rxd gnd scs sck miso mosi save pin 1 i.c. bottom side vst v20 i.c. busp rtxh rtxl busn 1 ep 25 26 27 28 29 30 31 32 16 15 14 13 12 11 10 9 otemp reset i.c. aout setvcc v33i wk creg xtal extal int bs1 bs0 vio vcc sw 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 r tx r txl typical application circuit **1 d 1 busp c rec r tx crec rtxh rtxl busn extal xtal gnd rxd txd vio set_vcc e981.03 u a r t c a p p l i ca t i o n bus coupling module vcc r set tp1-256 + - u 1 c 33i c st c vcc c cvcc d sps l sps v33i vst sw vcc c cst c 20 v20 20v c vio q functional diagram **2 (5) setvcc e981.03 (2) reset (1) otemp clock system knx / eib interface uart host interface (12) busp (8) crec (11) rtxh (10) rtxl (9) busn (23) extal (24) xtal (27) gnd (26) rxd (25) txd (19) vio (31) miso / gpio (30) mosi / gpio (29) sck / gpi (28) scs / gpi spi host interface c v20 (3) i.c. (13) i.c. ic supply ic start-up 20v supply current limiter adc/dac internal logic (21) bs1 (20) bs0 (32) save (4) aout monitoring unit (22) int mode control (7) wk / gpi switched power supply c 33i c st c vcc c cvcc d sps l sps (6) v33i (15) vst (17) sw vcc c cst (14) v20 (16) i.c. r vcc (18) vcc v20 d 1 c rec r tx + - u 1 q tp1-256 + - minimal function of e981.03 **3 bus coupling module u ar t h o s t p ro ce sso r o p t i o n a l o p t o - co u p l e r application module q u 1 c cst c st r tx c rec c 33i c vcc c cvcc d sps l sps r vcc c vio d 1 d vio r set v vio = v vcc (50ma) setvcc=v io q v vio v vio o t e m p i n t b s 0 v i o v c c s w x t a l e x t a l b s 1 gnd scs sck miso mosi txd rxd e l a - 0 1 2 0 33 v 3 3 i a o u t i . c. r e s e t v20 c r e c w k vst i.c. e9 8 1 . 0 3 busn rtxl rtxh busp 16 15 14 13 12 11 10 9 25 26 27 28 29 30 31 32 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 2 3 4 5 6 7 8 s e t v c c gnd mosi txd e l a - 0 1 2 0 33 i.c. e981.03 rtxl 16 15 14 13 12 11 10 9 25 26 27 28 29 30 31 32 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 2 3 4 5 6 7 8 save ic1 r txl full normal mode application **4 bus coupling module o p t i o n a l o p t o - c o u p l e r o p t i o n a l o p t o - c o u p l e r v vio u ar t h o st p ro ce ss o r s pi o p t i o n o p t i o n a l o p t o - c o u p l e r gpio analog in gpio / resetn gpio o p t i o n a l o p t o co u p l e r gpio vcc= 3.3v vcc= 5v open= alarm v v20 =20v / 20ma v vcc v vio gpio o p t i o n a l o p t o - c o u p l e r u 1 c cst c st c rec c 33i c vcc c cvcc d sps l sps r vcc c vio d 1 d vio r set q v vcc = 3.3v (50ma) setvcc=gnd v vcc = 5v (30ma) setvcc=v vio o t e m p i n t b s 0 v i o v c c s w x t a l e x t a l b s 1 gnd scs sck miso mosi txd rxd e l a - 0 1 2 0 33 v 3 3 i a o u t i . c. r e s e t v20 c r e c w k vst i.c. e9 8 1 . 0 3 busn rtxl rtxh busp 16 15 14 13 12 11 10 9 25 26 27 28 29 30 31 32 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 2 3 4 5 6 7 8 s e t v c c gnd mosi txd e l a - 0 1 2 0 33 i.c. e981.03 rtxl 16 15 14 13 12 11 10 9 25 26 27 28 29 30 31 32 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 2 3 4 5 6 7 8 save ic1 c 20 o p t i o n a l i so l a t i o n a m p l i f i e r r txl r tx l elmos semiconductor ag data sheet qm-no.: 25ds0046e.03 production data - jan 15, 2015 elmos semiconductor ag reserves the right to change the detail specifcations as may be required to permit improvements in the design of its products. knx / eib transceiver e981.03 e981.03
3/51 pin description pin name type 1) pull description 1 otemp d_o - over-temperature warning 2 reset d_io up bidirectional reset pin (low active) 3 i.c. - - reserved for factory use, connect to gnd during operation. 4 aout a_o - analog multiplexer output 5 setvcc d_i 2) combination of - selection of the vcc output voltage and - alarm function activation 6 v33i s - 3.3v internal supply: connect to external capacitor 7 wk hv_d_io - output with tri-state capability; used for knx telegram trigger output [default]: vio related output levels input: vst tolerant. thresholds v v33i related 8 crec hv_a_i - receive pin for knx bus communication 9 busn s - connection to the negative bus line 10 rtxl hv_a_io - ground connection of external resistor rtx 11 rtxh hv_a_io - knx send output pin - upper connection of external resistor rtx 12 busp hv_s - connection to positive knx bus via external diode for reverse polar - ity protection 13 i.c. - - reserved for factory use, connect to gnd during operation. 14 v20 hv_s - 20v dc supply output 15 vst hv_s - connection to external storage capacitor cst 16 i.c. - - do not connect externally 17 sw hv_a_io - switched output of dc/ dc converter 18 vcc a_i - dc/ dc converter output voltage control input 19 vio s - supply for digital io pins (connect to vcc if no external supply is used) 20 bs0 d_i down baud rate select pin 0 21 bs1 d_i down baud rate select pin 1 22 int d_o - used for knx collision trigger (low active) 23 extal d_o - external crystal terminal 2 24 xtal d_i - external crystal terminal 1 or clock input if no crystal is connected 25 txd d_o - uart transmit signal: from e981.03 to host processor (push/pull) 26 rxd d_i down uart receive signal: from host processor to e981.03 27 gnd s - gnd pin 28 scs d_i up spi chip select (low active) or g eneral p urpose i nput if spi is disabled 29 sck d_i down spi clock or gpi if spi is disabled 30 miso d_io - spi master in slave out data line or gpio if spi is disabled 31 mosi d_io - spi master out slave in data line or gpio if spi is disabled 32 save d_o up vst under voltage pre alarm signal (low active) 33 ep exposed die pad 1) d = digital, a = analog, s = supply, i = input, o = output, hv = high voltage 2) internally weak pulled to v33i/2. a open pin is the alarm condition. to select a vcc voltage push it to vio or pull it to gnd. elmos semiconductor ag data sheet qm-no.: 25ds0046e.03 production data - jan 15, 2015 elmos semiconductor ag reserves the right to change the detail specifcations as may be required to permit improvements in the design of its products. knx / eib transceiver e981.03
4/51 1 absolute maximum ratings stresses beyond these absolute maximum ratings listed below may cause permanent damage to the device. these are stress rat - ings only; operation of the device at these or any other conditions beyond those listed in the operational sections of this document is not implied. exposure to absolute maximum rated conditions for extended periods may affect device reliability. all voltages with respect to ground. currents fowing into terminals are positive, those drawn out of a terminal are negative. description symbol min max unit busp voltage v busp -0.3 55 v busp voltage during surge pulse (t < 150s) v busp_surge -0.3 65 v junction temperature t j -45 150 c storage temperature t s -45 150 c esd immunity (human body model, this test can be ap - plied between any two pins of the ic) v esd,hbm -2 2 kv voltage at digital and analog vio pins: reset , save , xtal, int , setvcc, otemp, scs , sck, mosi, miso, rxd, txd, bs0, bs1, aout v -0.3 v v io + 0.3 v voltage at wk pin v wk -0.3 40 v voltage at vst pin v vst -0.3 40 v voltage at sw pin v sw -5 v v st + 0.3 v voltage at vcc pin v vcc -0.3 8 v voltage at vio pin v vio -0.3 7 v overall current through digital and analog vio pins (latch up immunity): reset , save , xtal, int , setvcc, otemp, scs , sck, mosi, miso, rxd, txd, bs0, bs1, wk, aout i -100 100 ma current through digital and analog vio pins (latch up immunity): reset , save , xtal, int , setvcc, otemp, scs , sck, mosi, miso, rxd, txd, bs0, bs1, wk i -70 70 ma voltage at pin extal v extal -0.3 +3.6 v input voltage at crec pin v crec -15 v v busp voltage at pins rtxh, rtxl v rtx -0.3 v v busp current through rtxl pin i rtxl 0 800 ma current through aout pin i aout -10 10 ma voltage at pin v33i pin v v33i -0.3 +3.6 v voltage at pin v20 v v20 -0.3 v v st + 0.3 v 2 recommended operation conditions description condition symbol min typ max unit ambient temperature t amb -25 25 85 c external storage capacitance 4) c st 270 330 1000 f c st equivalent series resistance r esr,cst 0.1 1 c st voltage capability v cst 35 v parallel ceramic capacitance vst to gnd c cer,st 80 100 120 nf average bus idle voltage v busp 20 30 33 v 20v supply external capacitance 7) c 20 10 22 f c20 equivalent series resistance r esr,c20 0.1 1 elmos semiconductor ag data sheet qm-no.: 25ds0046e.03 production data - jan 15, 2015 elmos semiconductor ag reserves the right to change the detail specifcations as may be required to permit improvements in the design of its products. knx / eib transceiver e981.03
5/51 1) for telegram rates > 50% p rtx = 2 w is recommended. 2) the lower limit is necessary for dc/ dc control. the upper limit is a result of ripple considerations: voltage ripple is esr * current ripple of lsps. to guarantee this over lifetime it is useful to use a low esr capacitor and realize the lower limit with a series resistor. 3) i sat,sps is the dc current that causes an inductance drop of 20 %. 4) smaller c st down to 47 f can be used, however the load step capability has to be proved experimentally. 5) only necessary in case of the e981.03 being connected to a separate application module. these components only ensuring to meet the absolute maximum rating in case of connecting and disconnecting the application module. if the connector guarantees to connect gnd potential frst, the esd protection is not needed. 6) for better elaboration of the adc results a stable vio is highly recommended. 7) high capacitance may affect the reset / power up sequence time, as it is loaded with current limitation i v20(max) . 8) to use the maximum current capability on vcc and v20 it is needed to change max_bus_curr settings before switching on high current consumption. additionally a continuous under voltage condition on busp could reduce available current. to prevent unexpected under voltage conditions it is strongly recommended to observe vvst and implement a power management system. the voltage vvst could be observed adc converted trough uart or spi. for details read chapter 6.3 and 10.2 . description condition symbol min typ max unit 20v load current, this current is positive from the supply to the output i v20 8) 0 20 ma v cc output capacitance l sps =330h c vcc,l330 10 47 0.6 c st f v cc output capacitance l sps =1000h c vcc,l1000 68 100 0.6 c st f c vcc equivalent series resistance l sps =330h 2) r esr,cvcc,l330 0.2 0.5 0.8 c vcc equivalent series resistance l sps =1000h 2) r esr,cvcc, l1000 1 1.25 1.5 ceramic capacitance v cc to ground c cvcc 80 100 120 nf dc / dc converter inductance l sps 270 330 1200 h l sps series resistance r l,sps 1 3 10 saturation current of l sps 3) i sat,sps 160 ma maximum forward voltage of the external diode i=150ma v f,dsps 0.6 1 v reverse recovery time of the external diode t rr,dsps 50 ns v cc load current in 3.3 v mode, this current is positive from the supply to the output l sps =330h i vcc3.3,l330 8) 0 50 ma v cc load current in 3.3 v mode, this current is positive from the supply to the output l sps =1000h i vcc3.3,l1000 8) 0 70 ma v cc load current in 5v mode, this current is positive from the supply to the output l sps =330h i vcc5,l330 8) 0 30 ma v cc load current in 5v mode, this current is positive from the supply to the output l sps =1000h i vcc5,l1000 8) 0 70 ma digital io interface voltage 6) v io,norm =5v v io,5 4.75 5.25 v digital io interface voltage 6) v io,norm =3.3v v io,33 3.15 3.45 v crystal frequency (+- 50 ppm) f q 7.3728 mhz synchronization clock frequency applied at pin xtal no crystal in - stalled f xtal,sync 126.537 126.562 126.588 hz receiver decoupling capacitance c crec 50 56 62 nf external send resistance r tx 44.5 47 49.4 external send resistor power dissipation 1) p rtx 1 w system level esd protection resistance 5) r set; r vcc 1 k system level esd protection zener-diode 5) v zdiode 6.2 v analog monitor (aout - pin) current i aout -50 50 a external send pull-down r txl 9 10 11 k elmos semiconductor ag data sheet qm-no.: 25ds0046e.03 production data - jan 15, 2015 elmos semiconductor ag reserves the right to change the detail specifcations as may be required to permit improvements in the design of its products. knx / eib transceiver e981.03
6/51 (v busp = 19v 33v, t amb = -25c +85c, unless otherwise noted. positive currents are fowing into the device pins. typical values are at t amb = +25c, unless otherwise noted.) description condition symbol min typ max unit e981.03 modes, sequences and functions - dc characteristics voltage level at v33i pin for activating hard reset mode v v33i,reset,act 2.6 voltage level at v33i pin for leav - ing hard reset mode v v33i,reset,deact 3.0 first voltage level at vst pin for switching vcc supply on v st,vcc,on,abs 16 v second voltage level at vst pin for switching vcc supply on v vst,vcc,on,rel - v busp,mean - 6 v - v voltage level for switching knx ic current from busp to vst v vst,v33ana - 12 - v voltage level for switching vst load current in soft start mode to maximum level v vst,v33dig 15 v current at busp during soft start i busp,ss 9 10 ma voltage level at vst pin for switching vcc supply off v vst,vcc,off 9 v voltage level at vcc pin for reset deactivation (3.3 v) v vcc = 3.3 v v reset ,lh,3 2.8 3.05 v voltage level at vcc pin for reset deactivation (5v) v vcc = 5 v v reset ,lh,5 4.20 4.5 v voltage hysteresis at vcc pin for reset generation v reset ,vcc,hyst 0.095 v voltage level at vst pin for activa - tion of save pin v vst, save ,hl 13 15 v absolute v vst level for deactivation of save pin v vst ,save ,lh,abs 14 16 v relative v vst level for deactivation of save pin v vst, save ,lh,rel v busp,mean - 6 v v v busp level for deactivation of save pin v busp, save ,lh 18.5 v hysteresis of save pin activation / deactivation levels v st, save ,hyst 1 v save output voltage at logic-level low i save = 5 ma v io = 5 v v save ,low,5 0.7 v i save = 2 ma v save ,low,2 0.4 v pull up current at pin save v save = 0 v v io = 5 v i save ,pu -500 a absolute v 20 supply activation threshold v v20,on,abs v vst,save,lh +1 v relative v 20 supply activation threshold v v20,on,rel v busp,mean - 5 v absolute v 20 supply deactivation threshold v v20,off,abs v vst,save,hl +1 v 3 electrical characteristics elmos semiconductor ag data sheet qm-no.: 25ds0046e.03 production data - jan 15, 2015 elmos semiconductor ag reserves the right to change the detail specifcations as may be required to permit improvements in the design of its products. knx / eib transceiver e981.03
7/51 description condition symbol min typ max unit relative v20 supply deactivation threshold v v20,off,rel v busp,mean - 6 v high threshold at pin wk. 1) v wk,high 2.0 2.5 v low threshold at pin wk. 1) v wk,low 1.1 1.6 v pull down current at pin wk (active in input mode) 1) v wk = v vio /2, v vio = 5v i wk,pd 60 a high level at pin wk i wk = -2ma v wk,out,high2 v vio -1v v high level at pin wk i wk = -0.5ma v wk,out,high5 v vio -0.5v v low level at pin wk i wk = 5ma v wk,out,low 0.7 v e981.03 mode parameters - ac characteristics maximum duration of hard reset mode v busp > 20 v c 33i = 100 nf t 33i,on 20 ms wait time between knx bus com - munication free and sending reset indication to the host processor t w,ri 40 bit times duration of an active driven wake- up pulse to mcu causes by a valid trigger telegram t trigger,pw 80 100 120 ms debounce time of alarm condition at pin setvcc t alarm,deb 100 120 ms reset concept - dc characteristics actively driven low level on pin reset i reset < 5 ma v vio > 3 v v reset ,low, out 0.4 v pull up current at pin reset 2) v reset = 0 v v vio = 5 v i reset ,pu -500 a low level at pin reset input path v reset , low,in 0.2 v io high level at pin reset input path v reset , high,in 0.8 v io minimum voltage at pin vio for in - terpreting the input path of reset 3) v io,min, reset 2.0 v reset concept - ac characteristics debounce time of input pin reset for activation soft reset mode t reset,deb 10 s minimum active time of reset 4) t reset,min 10 20 ms power supply C dc characteristics voltage drop between bsup and vst pin v st_drop 2 2.4 3 v maximum dc busp current max_bus_curr (0x20f) = 0xbf i busp(max) 11.4 12 12.6 ma electrical characteristics (continued) (v busp = 19v 33v, t amb = -25c +85c, unless otherwise noted. positive currents are fowing into the device pins. typical values are at t amb = +25c, unless otherwise noted.) 1) the wk pin is confgurable as input or as output which sent a trigger pulse on received trigger telegram. to confgure this change bit en_out to 0 in register trigger (0x214). default confguration is output. 2) the reset pin is an open drain input/output with pull current source to v io 3) the input at pin reset is not active in reset and startup modes and in case of low v io 4) in case of reset activation by e981.03. elmos semiconductor ag data sheet qm-no.: 25ds0046e.03 production data - jan 15, 2015 elmos semiconductor ag reserves the right to change the detail specifcations as may be required to permit improvements in the design of its products. knx / eib transceiver e981.03
8/51 description condition symbol min typ max unit maximum dc busp current max_bus_curr (0x20f) = 0xff i busp(max) 17.1 18 18.9 ma maximum dc busp current max_bus_curr (0x20f) = 0x3f i busp(max) 22.8 24 25.2 ma maximum dc busp current max_bus_curr (0x20f) = 0x7f i busp(max) 28.5 30 31.5 ma maximum bus current slope in 0.25 ma/ms mode current_slope (0x210) = 0x00 slope, lim025_di/ dt 0.17 0.2 0.23 ma / ms maximum bus current slope in 0.5 ma/ms mode (default) (0x210) = 0x01 slope, lim05_di/dt 0.35 1) 0.4 1) 0.45 1) ma / ms maximum bus current slope in 1.25 ma/ms mode (0x210) = 0x02 slope, lim125_di/ dt 0.87 1) 1 1) 1.13 1) ma / ms maximum bus current slope in 2.5 ma/ms mode (0x210) = 0x03 slope, lim25_di/dt 1.75 2 2.25 ma / ms output voltage at pin v20 v vst > 20v, i v20 = 0 ... i v20(max) (positive output current) v v20 18.5 20 21.5 v voltage drop linear voltage regulator at under-voltage v vst <20v, i v20 =0...20ma (positive output current) v v20,drop 0.5 0.8 v short circuit current (positive output cur - rent) i v20(sc) 25 50 ma output voltage in 3.3v mode i load,vcc <= 50 ma (positive output cur - rent) setvcc = gnd v vcc3.3 3.15 3.3 3.45 v output voltage in 5v mode i load,vcc <= 30 ma (pos - itive output current) setvcc = vio v vcc5 4.75 5 5.25 v voltage ripple in 3.3v mode. this ripple is already included in output voltage tolerance. cvcc = 47f esr = 0.5 lsps = 330h rlsps = 3 setvcc = gnd v vcc,pp3.3 70 mv voltage ripple in 5v mode. this rip - ple is already included in output voltage tolerance. cvcc = 47f esr = 0.5 lsps = 330h rlsps = 3 setvcc = vio v vvc,pp5 70 mv voltage at pin setvcc for selection of vcc = 3.3 v and no active alarm condition v setvcc,low 0.6 v voltage at pin setvcc for an active alarm condition v setvcc,alarm 0.4 0.6 v v33i electrical characteristics (continued) (v busp = 19v 33v, t amb = -25c +85c, unless otherwise noted. positive currents are fowing into the device pins. typical values are at t amb = +25c, unless otherwise noted.) 1) guaranteed by design elmos semiconductor ag data sheet qm-no.: 25ds0046e.03 production data - jan 15, 2015 elmos semiconductor ag reserves the right to change the detail specifcations as may be required to permit improvements in the design of its products. knx / eib transceiver e981.03
9/51 electrical characteristics (continued) description condition symbol min typ max unit voltage at pin setvcc for selection of vcc = 5 v and no active alarm condition v setvcc,high 0.8 v v33i pull resistance at pin setvcc to v33i r p33,setvcc 200 k pull resistance at pin setvcc to gnd r p0,setvcc 200 k voltage at pin v33i v v33i 3.22 3.3 3.38 v clock system - ac characteristics crystal frequency (50ppm) clk_fac l/h (0x20a / 0x20b) = 0xe330 (reset value) f q 7.3728 mhz synchronization clock frequency applied at pin xtal no crystal installed extal is n.c. f xtal,sync 126.537 126.562 126.588 hz host uart interface - dc characteristics input low voltage at pin rxd v rxd,low 0.2 v io input high voltage at pin rxd v rxd,high 0.8 v io pull down current at pin rxd v rxd = 5 v, v io = 5 v i rxd,pd 100 a low level on txd pin i txd = 5 ma, v io = 5 v txd,low,5 0.7 v i txd = 2 ma v txd,low,2 0.4 v high level on txd pin i txd = -5 ma, v io = 5 v txd,high,5 v io -0.7 v i txd = -2 ma v txd,high,2 v io -0.4 v low level on pin bs0 v bs0,low 0.2 v io high level on pin bs0 v bs0,high 0.8 v io pull down current on pin bs0 v io =5 v, v bs0 =5 v i pd,bs0 30 a low level on pin bs1 v bs1,low 0.2 v io high level on pin bs1 v bs1,high 0.8 v io pull down current on pin bs1 v io =5 v, v bs0 =5 v i pd,bs1 30 a host uart interface - ac characteristics uart receiver timeout between subsequent byte of a service t uart,ibg,rx 2.5 ms baud rate deviation f uart -3% 3% host sp interface - dc characteristics input high voltage at pin scs, sck, mosi, miso v spi ,high 0.8 v io input low voltage at pin scs, sck, mosi, miso v spi ,low 0.2 v io pull down current on pin scs v scs =5 v, v io =5 v i pu, scs -30 a pull down current on pin sck v sck =5 v, v io =5 v i pu,sck -30 a high output level on miso, mosi pin i miso = -5ma, v io = 5v v miso,high,5 v io -0.7v i miso = -2 ma v miso,high,2 v io -0.4 v low output level on miso, mosi pin i miso = 5ma, v io = 5v v miso,low,5 0.7 v i miso = 2 ma v miso,low,2 0.4 v (v busp = 19v 33v, t amb = -25c +85c, unless otherwise noted. positive currents are fowing into the device pins. typical values are at t amb = +25c, unless otherwise noted.) elmos semiconductor ag data sheet qm-no.: 25ds0046e.03 production data - jan 15, 2015 elmos semiconductor ag reserves the right to change the detail specifcations as may be required to permit improvements in the design of its products. knx / eib transceiver e981.03
10/51 description condition symbol min typ max unit host sp interface - ac characteristics time between falling scs edge and frst rising sck edge t ls1 30 ns time between last falling sck edge and rising scs edge t ls2 30 ns inter byte gap - time between last falling sck edge of a byte transmission and frst rising sck edge of subsequent byte within a spi transfer relevant especially for read accesses between address and data bytes t ibg 1 s period of spi clock t p_ sck 250 ns mosi data setup time (time be - tween mosi data valid and falling edge of sck t setup 30 ns input low voltage at pin mosi data hold time (time between falling edge of sck and mosi data invali - dation) t hold 20 ns miso data valid time (time be - tween rising edge of sck and miso data valid) c miso < 20 pf t valid 35 ns time between rising edge of scs and high impedance at miso t miso_z 100 ns monitoring functions adc scaling factor for low voltage v busp signal used for measurement (v adc / v busp ) scale vbusp, adc 1/16.1 1/15 1/13.9 adc scaling factor for low voltage v 20 signal used for measurement (v adc / v 20 ) scale v20,adc 1/8.4 1/8 1/7.6 adc scaling factor for low voltage v cc signal used for measurement (v adc / v cc ) scale vcc,adc 1/2.14 1/2 1/1.86 adc scaling factor for low voltage v cc signal used for measurement (v adc / v st ) scale vst,adc 1/10.7 1/10.05 1/9.4 adc scaling factor for low voltage v io signal used for adc measurement (v adc / v io ) scale vio,adc 1/2.36 1/2.2 1/2.04 averaging time for mean value of v busp t vbusp(av) 5 ms temperature limit for activating temperature warning t warn,on 110 120 140 c temperature limit for deactivating temperature warning t warn,off t warn,on -10c c temperature limit for reducing power consumption t shutoff,on t warn,on +30c c electrical characteristics (continued) (v busp = 19v 33v, t amb = -25c +85c, unless otherwise noted. positive currents are fowing into the device pins. typical values are at t amb = +25c, unless otherwise noted.) elmos semiconductor ag data sheet qm-no.: 25ds0046e.03 production data - jan 15, 2015 elmos semiconductor ag reserves the right to change the detail specifcations as may be required to permit improvements in the design of its products. knx / eib transceiver e981.03
11/51 electrical characteristics (continued) pins of spi and uart interfaces, save , reset , wk, int and otemp are prepared for galvanic insulation with optical coupler. miso, txd, save , reset , wk, int and otemp can provide a current of 5 ma for driving a diode of an opti - cal coupler in case of vio = 5 v. for lower power consumption set vio_sw bit in ps_ctrl register. remark! the layout example is incomplete! the layout only gives an example about the placement of the dc/dc converter components, the external capacitors and gnd routing. description condition symbol min typ max unit temperature limit for switching on power consuming functions t shutoff,off t warn,on +20c c high level at pin otemp i otemp = -5 ma, v vio =5v v otemp,high,5 v io -0.7v i otemp = -2 ma v otemp,high,2 v io -0.4v low level at pin otemp i otemp = 5 ma, v vio =5v v otemp,low,5 0.7 v i otemp = 2 ma v otemp,low,2 0.4 v temperature step per lsb t lsb 2.5 k aout scaling factor for low voltage vbusp signal used for measure - ment (v aout / v busp ) scale vbusp, aout,3v3 1/12.2 1/12 1/11.8 aout scaling factor for low voltage vbusp signal used for measure - ment (v aout / v busp ) scale vbusp, aout,5v 1/8.1 1/8 1/7.9 4 hardware confguration (v busp = 19v 33v, t amb = -25c +85c, unless otherwise noted. positive currents are fowing into the device pins. typical values are at t amb = +25c, unless otherwise noted.) 4.1 pcb design rules figure 1. pcb layout elmos semiconductor ag data sheet qm-no.: 25ds0046e.03 production data - jan 15, 2015 elmos semiconductor ag reserves the right to change the detail specifcations as may be required to permit improvements in the design of its products. knx / eib transceiver e981.03
12/51 dc/ dc converter active (3.3 v): i max =50 ma setvcc = gnd: vcc = 3.3 v bs1 = bs0 = gnd: uart 19.2 k baud v20 not used: v20 = vst uart optional with optical coupler spi not used mosi = gnd miso = open sck = gnd scs = vio otemp not used: open wk not used: open save not used: open reset not used: open aout not used: open 4.2 minimal function of e981.03 figure 2. schematic example (minimal application) r tx r txl typical application circuit **1 d 1 busp c rec r tx crec rtxh rtxl busn extal xtal gnd rxd txd vio set_vcc e981.03 u a r t c a p p l i ca t i o n bus coupling module vcc r set tp1-256 + - u 1 c 33i c st c vcc c cvcc d sps l sps v33i vst sw vcc c cst c 20 v20 20v c vio q functional diagram **2 (5) setvcc e981.03 (2) reset (1) otemp clock system knx / eib interface uart host interface (12) busp (8) crec (11) rtxh (10) rtxl (9) busn (23) extal (24) xtal (27) gnd (26) rxd (25) txd (19) vio (31) miso / gpio (30) mosi / gpio (29) sck / gpi (28) scs / gpi spi host interface c v20 (3) i.c. (13) i.c. ic supply ic start-up 20v supply current limiter adc/dac internal logic (21) bs1 (20) bs0 (32) save (4) aout monitoring unit (22) int mode control (7) wk / gpi switched power supply c 33i c st c vcc c cvcc d sps l sps (6) v33i (15) vst (17) sw vcc c cst (14) v20 (16) i.c. r vcc (18) vcc v20 d 1 c rec r tx + - u 1 q tp1-256 + - minimal function of e981.03 **3 bus coupling module u ar t h o s t p ro ce sso r o p t i o n a l o p t o - co u p l e r application module q u 1 c cst c st r tx c rec c 33i c vcc c cvcc d sps l sps r vcc c vio d 1 d vio r set v vio = v vcc (50ma) setvcc=v io q v vio v vio o t e m p i n t b s 0 v i o v c c s w x t a l e x t a l b s 1 gnd scs sck miso mosi txd rxd e l a - 0 1 2 0 33 v 3 3 i a o u t i . c. r e s e t v20 c r e c w k vst i.c. e9 8 1 . 0 3 busn rtxl rtxh busp 16 15 14 13 12 11 10 9 25 26 27 28 29 30 31 32 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 2 3 4 5 6 7 8 s e t v c c gnd mosi txd e l a - 0 1 2 0 33 i.c. e981.03 rtxl 16 15 14 13 12 11 10 9 25 26 27 28 29 30 31 32 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 2 3 4 5 6 7 8 save ic1 r txl full normal mode application **4 bus coupling module o p t i o n a l o p t o - c o u p l e r o p t i o n a l o p t o - c o u p l e r v vio u ar t h o st p ro ce ss o r s pi o p t i o n o p t i o n a l o p t o - c o u p l e r gpio analog in gpio / resetn gpio o p t i o n a l o p t o co u p l e r gpio vcc= 3.3v vcc= 5v open= alarm v v20 =20v / 20ma v vcc v vio gpio o p t i o n a l o p t o - c o u p l e r u 1 c cst c st c rec c 33i c vcc c cvcc d sps l sps r vcc c vio d 1 d vio r set q v vcc = 3.3v (50ma) setvcc=gnd v vcc = 5v (30ma) setvcc=v vio o t e m p i n t b s 0 v i o v c c s w x t a l e x t a l b s 1 gnd scs sck miso mosi txd rxd e l a - 0 1 2 0 33 v 3 3 i a o u t i . c. r e s e t v20 c r e c w k vst i.c. e9 8 1 . 0 3 busn rtxl rtxh busp 16 15 14 13 12 11 10 9 25 26 27 28 29 30 31 32 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 2 3 4 5 6 7 8 s e t v c c gnd mosi txd e l a - 0 1 2 0 33 i.c. e981.03 rtxl 16 15 14 13 12 11 10 9 25 26 27 28 29 30 31 32 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 2 3 4 5 6 7 8 save ic1 c 20 o p t i o n a l i so l a t i o n a m p l i f i e r r txl r tx l elmos semiconductor ag data sheet qm-no.: 25ds0046e.03 production data - jan 15, 2015 elmos semiconductor ag reserves the right to change the detail specifcations as may be required to permit improvements in the design of its products. knx / eib transceiver e981.03
13/51 4.3 full normal mode application figure 3. schematic example (full application) dc/dc converter active (3.3 v/5 v): i max = 50/ 30 ma setvcc = gnd: vcc = 3 v setvcc = vio: vcc = 5 v bs1 = bs0 = gnd: uart 19.2 k baud v20 used: additional c v20 , i max = 20 ma uart optional with optical coupler spi optional with optical coupler in normal mode alarm functionality is usable. alarm is detected in case of an open setvcc pin. for other schematics read application notes. otemp used optional with optocoupler wk used optional with optocoupler save used optional with optocoupler reset used optional with optocoupler aout used optional with insulation amplifer for analog signal r tx r txl typical application circuit **1 d 1 busp c rec r tx crec rtxh rtxl busn extal xtal gnd rxd txd vio set_vcc e981.03 u a r t c a p p l i ca t i o n bus coupling module vcc r set tp1-256 + - u 1 c 33i c st c vcc c cvcc d sps l sps v33i vst sw vcc c cst c 20 v20 20v c vio q functional diagram **2 (5) setvcc e981.03 (2) reset (1) otemp clock system knx / eib interface uart host interface (12) busp (8) crec (11) rtxh (10) rtxl (9) busn (23) extal (24) xtal (27) gnd (26) rxd (25) txd (19) vio (31) miso / gpio (30) mosi / gpio (29) sck / gpi (28) scs / gpi spi host interface c v20 (3) i.c. (13) i.c. ic supply ic start-up 20v supply current limiter adc/dac internal logic (21) bs1 (20) bs0 (32) save (4) aout monitoring unit (22) int mode control (7) wk / gpi switched power supply c 33i c st c vcc c cvcc d sps l sps (6) v33i (15) vst (17) sw vcc c cst (14) v20 (16) i.c. r vcc (18) vcc v20 d 1 c rec r tx + - u 1 q tp1-256 + - minimal function of e981.03 **3 bus coupling module u ar t h o s t p ro ce sso r o p t i o n a l o p t o - co u p l e r application module q u 1 c cst c st r tx c rec c 33i c vcc c cvcc d sps l sps r vcc c vio d 1 d vio r set v vio = v vcc (50ma) setvcc=v io q v vio v vio o t e m p i n t b s 0 v i o v c c s w x t a l e x t a l b s 1 gnd scs sck miso mosi txd rxd e l a - 0 1 2 0 33 v 3 3 i a o u t i . c. r e s e t v20 c r e c w k vst i.c. e9 8 1 . 0 3 busn rtxl rtxh busp 16 15 14 13 12 11 10 9 25 26 27 28 29 30 31 32 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 2 3 4 5 6 7 8 s e t v c c gnd mosi txd e l a - 0 1 2 0 33 i.c. e981.03 rtxl 16 15 14 13 12 11 10 9 25 26 27 28 29 30 31 32 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 2 3 4 5 6 7 8 save ic1 r txl full normal mode application **4 bus coupling module o p t i o n a l o p t o - c o u p l e r o p t i o n a l o p t o - c o u p l e r v vio u ar t h o st p ro ce ss o r s pi o p t i o n o p t i o n a l o p t o - c o u p l e r gpio analog in gpio / resetn gpio o p t i o n a l o p t o co u p l e r gpio vcc= 3.3v vcc= 5v open= alarm v v20 =20v / 20ma v vcc v vio gpio o p t i o n a l o p t o - c o u p l e r u 1 c cst c st c rec c 33i c vcc c cvcc d sps l sps r vcc c vio d 1 d vio r set q v vcc = 3.3v (50ma) setvcc=gnd v vcc = 5v (30ma) setvcc=v vio o t e m p i n t b s 0 v i o v c c s w x t a l e x t a l b s 1 gnd scs sck miso mosi txd rxd e l a - 0 1 2 0 33 v 3 3 i a o u t i . c. r e s e t v20 c r e c w k vst i.c. e9 8 1 . 0 3 busn rtxl rtxh busp 16 15 14 13 12 11 10 9 25 26 27 28 29 30 31 32 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 2 3 4 5 6 7 8 s e t v c c gnd mosi txd e l a - 0 1 2 0 33 i.c. e981.03 rtxl 16 15 14 13 12 11 10 9 25 26 27 28 29 30 31 32 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 2 3 4 5 6 7 8 save ic1 c 20 o p t i o n a l i so l a t i o n a m p l i f i e r r txl r tx l elmos semiconductor ag data sheet qm-no.: 25ds0046e.03 production data - jan 15, 2015 elmos semiconductor ag reserves the right to change the detail specifcations as may be required to permit improvements in the design of its products. knx / eib transceiver e981.03
14/51 the knx / eib - interface is a full compatible knx tp1 transceiver with autonomous medium access control and individual physical address. the telegram on knx bus is analyzed and dependent on its contents and the e981.03 has a full duplex uart interface to trans - mit and receive bytes asynchronously. the protocol be - tween e981.03 and host controller is a two-wire proto - col with software handshake. the uart host interface consists of the following three parts ? uart physical layer realizes media access and bit decoding / encoding or output driver for knx by - pass in analog mode 1) only necessary in case of the e981.03 being connected to a separate application module. these components only ensuring to meet the absolute maximum rating in case of connecting and disconnecting the application module. if the connector guarantees to connect gnd potential frst, the esd protection is not needed. table 1. recommended components component recommended value remarks u1 model: smaj43ca, smbj43ca d1 model: byg21 c st 330 f / 35 v esr < 1 c cst ceramic 100 nf / 35 v 20% c 20 22 f / 35 v esr < 1 ohm l sps 330 h, r lsps ,typ = 3 ,r lsps,max = 10 , i sat,sps = 160 ma, t amb < 85 c 20% c vcc 47 f / 6 v 0.2 < esr < 0.8 c cvcc ceramic 100 nf / 8v 20% c cvio ceramic 100 nf / 8v 20% d sps 40 v, 200 ma, t rr < 15 ns e.g. bat64 c 33i ceramic 100 nf 20% r tx 47 5 % / 1 w c rec ceramic 56 nf 10 % q f = 7.3728 mhz, tolerance 50 ppm do not use external capaci - tors or crystals with internal capacitors. r set 1) 1 k r vcc 1) 1 k d vio 1) 6.2 v, 500 mw r txl 10 k 1% 5 interfaces description 5.1 knx / eib C interface communication mode, the data will be processed. in analog mode, the signals send and rec are directly bypassed to the host uart interface pins rxd and txd. 5.2 uart C interface ? uart logical layer provides byte framing capabili - ties ? uart service layer defnes control and data access sequences to secure uart communication, a crc calculation for receive and transmit path can be activated separately. elmos semiconductor ag data sheet qm-no.: 25ds0046e.03 production data - jan 15, 2015 elmos semiconductor ag reserves the right to change the detail specifcations as may be required to permit improvements in the design of its products. knx / eib transceiver e981.03
15/51 bs1 bs0 description crc check useable remark gnd vio 9.6 k baud no 8 bit, even parity, 1 stop-bit gnd gnd 19.2 k baud yes 8 bit, even parity, 1 stop-bit vio gnd 115.2 k baud yes 9 bit, even parity, 1 stop-bit vio vio analog mode no table 2. baud rate confguration 5.3 spi compatible C interface e981.03 has a slave spi compatible - interface to trans - mit and receive data. the interface can be used alterna - tively for e981.03 confguration and knx communica - tion. in analog mode the interface is the only possibility to confgure parameters like bus current. to secure spi compatible communication, a crc calcula - tion can also be activated. the bit d8 in 9-bit uart has the following meaning: 0: data byte 1: service byte after successful upload of the frame e981.03 sends the frame on knx bus after the knx specifed bus idle time detected. the repeat fag of the frame transmitted is handled by the e981.03. ? in frst transmission the repeat fag is set to 1. ? in repeated frames the repeat bit is cleared to 0. the acknowledge frame sent by the receivers of the frame is checked and ? in case of busy acknowledged frames e981.03 waits for at least 150 bit times after the busy ac - knowledge before starting a new transmission at - tempt. these 150 bit times refer to the end of the busy acknowledged frame independent from other communication on the eib bus. in case of bus com - the user could switch off the spi compatible - interface by setting on0 and on1 to zero (register spi_ctrl ). in this case 4 gpios could be used trough the uart C inter - face. the gpios have vio related i/o levels. the pins mosi and miso are useable as general purpose inputs or outputs. the pins scs and sck can be used as input pins. for read and write 5.4 telegram transmission munication between the two (busy) repetitions the time between the interposed frame and the busy repetition is 50 bit times. ? in case of nack acknowledged frames e981.03 starts a new transmission attempt. ? no acknowledge and corrupted acknowledge will be handled as nack. ? busy and nack acknowledge will be handled as busy. if the repeat fag in the uploaded frame is not set, e981.03 will send the frame only once even in case of not ack acknowledgment. the maximum number of repetitions is defned in the register max_rst_cnt and can be modifed e.g. by a host uart service or spi. s t d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 p s p s t s t a r t b i t l o w d 0 .. d 8 d a t a b i t s l s b ? r s t p p a r i t y b i t even s p s t o p b i t h i g h m s b i t s 0 4 2 , 1 1 1 1 0 4 = ? 1 9 . 2 0 0 ba u d s t d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 p s p m s b i t s 1 0 4 , 0 1 2 7 , 8 = ? d 8 m s b it s 5 2 1 , 0 1 1 5 2 = ? 9 . 6 0 0 ba u d 1 1 5 . 2 0 0 ba u d figure 4. uart bit elmos semiconductor ag data sheet qm-no.: 25ds0046e.03 production data - jan 15, 2015 elmos semiconductor ag reserves the right to change the detail specifcations as may be required to permit improvements in the design of its products. knx / eib transceiver e981.03
16/51 the pin aout is used to monitor several voltages. the source can be selected by a register value. the analog monitor signal is not fltered by the e981.03. especially the scaled analog bus voltage is not the mean value of the bus voltage but follows the busp line immediately. between aout buffer and aout pin a series resistor of approximately 10 k is implemented in e981.03. it can be the wk pin is confgurable as output for remote wake-up with trigger telegram or as general purpose input. to con - fgure as a input change bit en_out to 0 in register trigger (0x214). default confguration is output. to read input state read bit wk in the register pins . aout is controlled by register aout_ctrl and register aout_src . 5.5 aout used to realize a frst order rc flter by connecting aout to an external capacitor c ext . measurement of aout voltage needs to take the intern resistor value into ac - count (high impedance measurement input use). measurement values are: ? temperature voltage ? band gap voltage 1) ? bus voltage vio = 3.3 v vbus / 12 vio = 5 v vbus / 8 other multiplexer confguration are invalid 1) the band gap voltage can be used to increase the precision of the adc. figure 5. analog monitoring v bus /12 aout_ctrl[0] v bus /8 v temp 1 2 3 0 1 aout analog in external c e981.03 approx. 10k? v bg + - aout_src[0:1] description condition symbol min typ max unit time between end of telegram upload from host processor to e981.03 and start of telegram transmission on eib bus (in case of idle eib bus) bit txdel of register uart_ctrl = 0 l_data or l_polldata frame t tr,delay,var 104 s time between end of telegram upload from host processor to e981.03 and start of telegram transmission on eib bus (in case of idle eib bus) bit txdel of register uart_ctrl = 0 l_extdata frame 250 s wait time after busy acknowl - edge t busy,rep 104 s table 3. knx frame timing 5.6 wk elmos semiconductor ag data sheet qm-no.: 25ds0046e.03 production data - jan 15, 2015 elmos semiconductor ag reserves the right to change the detail specifcations as may be required to permit improvements in the design of its products. knx / eib transceiver e981.03
17/51 5.7 e981.03 system functions 5.8 power supply s w i t ch c: o p e n : w h en v vs t i s b e l o w v v2 0 , o f f , ab s o r v v2 0 , o ff, r e l v vs t < v v2 0 , o ff, a b s , t y p = v vs t , sa ve, h l , ty p + 1 v = 14 v + 1v = 15 v v vs t > v b u sp , m e a n - 6 v cl o s e: w h e n v vs t i s a b o ve e i t h er v v2 0 , o n , a b s a n d v v2 0 , o n , r e l v vs t > v v2 0 , o n , a b s , ty p = v vs t , sa ve, l h , a b s , t y p + 1 v = 15 v + 1v = 16 v v vs t > v vb u s p , m e a n - 5 v c 3 3 i c s t c v c c v 33 i ( 6 ) v s t ( 1 5) v c c ( 1 8) c v 2 0 v 20 ( 1 4) v 2 0 s u p p l y v 3 3 i s u p p l y v c c b u c k c o n v e r t e r s w i t ch a s w i t ch c d b u s p i v s t i v 2 0 i v 3 3 i i v c c s w i t ch b v v s t v v 2 0 v v 3 3 i v v c c v b u s p 1 2 s w i t ch a : s w i t ch t o 0 : o n l y a f t e r p o n u n t i l en d o f s o f t - s t ar t s w i t ch t o 1 : ( v vi o i s i n va l i d r an g e > ~ 3 . 1 ? < ~ 3. 4v ) an d ( v vc c i s 3 . 3 v o r ( v vc c = 5 v a n d p f ct rl ( 0 x 20 e ) bi t 7 i s s e t ) ) s w i t ch t o 2 : o t h er w i s e s w i t ch b: s w i t ch t o 1 : ( v vi o i s i n va l i d r an g e > ~ 3 . 1 ? < ~ 3. 4v ) an d ( v vc c i s 3 . 3 v o r ( v vc c = 5 v a n d p f ct rl ( 0 x 20 e ) bi t 7 i s s e t ) ) s w i t ch t o 2 : o t h e r w i s e 1 2 0 i f th e i lo a d _s u m i s h i g h e r th e n i b u s p , m a x th e c v s t d i s c h a r g e s a n d t h e v o l t a g e v v s t d r o p s d o w n . v v s t _ d r o p b us cu r r e n t sou r ce i r e f < = i b u s p ,m a x i l o a d _ s u m v c c ( 1 8) v io ( 1 9) c v i o o p t i o n 1 : v vi o s u p p l i e d b y v vc c o p t i o n 2 : v vi o s u p p l i e d b y ex t er n a l gnd figure 6. confgurable power management the supply blocks generates a 20v application volt - age v v20 , a variable storage voltage vst, a confgurable 5v/3.3v output voltage v vcc and a 3.3v voltage v v33i used by internal components of the e981.03. the voltages v v20 and v vcc can be used to supply external components. the voltages v v33i is externally blocked but the strictly recommendation is not use this pin for other supplies! the voltage v vst is externally blocked. usage of this volt - age for external supplies is not recommended because it disturb the autonomous power management of the ic! to prevent a overload and a fast load slope on the bus the power management of the ic generates a variable storage voltage v vst . this voltage has a limited input cur - rent i ref and a limited slope of i ref . the maximum current i ref and the maximum slope are confgurable through spi or uart C service. the value of v vst in normal operation without an overload condition is v busp C v vst_drop . the power which is continuously useable is (v busp C v vst_drop ) * i ref . if more power is used the c st is discharging, v vst drops below v busp C v vst_drop . to prevent a unpredictable crash the supplies have the following prioritization: 3 rd : v20 is generated by a linear voltage regulator out of the v st . it is the supply for additional circuits and has the low - est priority. v20 is the frst one drops down, to prevent a dropping down of vcc with the consequence of a mi - crocontroller reset. if a continuous overload is applied a pulsing v20 is possible. 2 nd : vcc is generated by a step down dc/dc converter and could supply a microcontroller with its peripheral. the output voltage is selectable 5v or 3.3v. the supply could deliv - er up to 30ma at 5v and 50ma at 3.3v. before it drops down v20 is switched of. if a continues overload condi - tion is active v vst drops below v vst,save,hl and the safe sig - nal fags a overload condition before vcc drops down. 1 st : v33i supplies the ic and is the last one which drops down. please refer the application note for more details. elmos semiconductor ag data sheet qm-no.: 25ds0046e.03 production data - jan 15, 2015 elmos semiconductor ag reserves the right to change the detail specifcations as may be required to permit improvements in the design of its products. knx / eib transceiver e981.03
18/51 the main clock is generated by an internal rc oscilla - tor. an external clock reference / crystal can be used to achieve a system clock accuracy of approx 0.05%. two different synchronization clocks are useable: 1) crystal at f q = 7.3728 mhz ? default confguration ? foot point capacitors are incl 2) clock reference at f xtal,sync = 126.562 hz ? the crystal oscillator should be switched off - ext_q to 1 in clk_ctrl register 5.9 clock system e x t a l x t a l q 1 1 0 o sc q o sc rc c xt al c ext al d i v i d e r d q p l l c l k spi a c l k c l k u ar t c l k kn x c l k m e m o ry e981.03 s y n c c l k in o p t i o n al : o pt o c o up l e r f x t a l , s y n c e . g . f r o m h o s t p r o c e s s o r x t a l cryst a l cl k s ou rce figure 7. clock generation the sync - signal source could be a crystal oscilla - tor (oscq) or an external vio related digital clock on xtal(remark: absolute maximum rating v). the ic au - tomatically detects the used mode and selects the cor - rect internal signal path. in analog mode no crystal and no external clock are re - quired. to increase the robustness to emi the input xtal shall be connected to gnd if not used. s a v e h a r d r e s e t s o f t s t a r t v 3 3 i n o t o k v 3 3 i o k s o f t s t ar t f in i sh e d r e se t c o n d it i o n v o lt a g e v s t n o t o k v o lt a g e v s t o k r e ce iv e t r ig g e r t ele g r am c o m m u n i c a t i o n m o d e e n d o f ala r m t e leg r a m t r a n s m it io n a l a r m m et a la r m c o n d it i o n 2 ) n o co n d it io n t r i g g e r 1 ) 6 mode depending device functions figure 8. device modes 1) trigger mode only available from normal mode 2) alarm mode not available in analog mode see chapter 6.5 analog mode elmos semiconductor ag data sheet qm-no.: 25ds0046e.03 production data - jan 15, 2015 elmos semiconductor ag reserves the right to change the detail specifcations as may be required to permit improvements in the design of its products. knx / eib transceiver e981.03
19/51 6.1 reset / power up-&down sequence 6.2 overall to ensure a stable function under all conditions the e981.03 supports several power up and power down scenarios. the status of the confgurable supply management/ monitoring can be queried via uart and digital save pin at any time. properties power up sequence ? hard reset mode v33i not ok ? start up mode external supply voltage switch on dependent on capacitance the power up sequence stays longer in this mode ? soft reset e981.03 will be set to soft reset value. power down sequence ? save mode save pin is active (low) ? internal reset hard reset mode with falling bus voltage (data point 1) vst falls, too. when v vst is below either v v20,off,abs or v v20,off,rel (whichev - er is higher) v20 is switched off (data point 2). v vst will rise in typical case of high v20 load resulting in pulsed activation of v20. when v vst falls below v vst,save,hl the save signal is ac - tivated to initiate the save routines of host processor (data point 3). the dc/dc converter continues its nor - mal operation until v vst falls below the minimum con - verter input voltage v vcc switch off and the v v33i input (or output compare figure 6 confgurable power man - agement ) make a switchover to v vst without a fail time (data point 4). to avoid bus overload soft start phase with bus current reduction is activated in case of ac - tive save . the reset signal is activated when v vcc falls below the 6.3 undervoltage condition threshold v reset ,hl (short after data point 4). if the busp recovers now (data point 5) the ic come back with - out internal reset. save will be deactivated, when v vst achieves the value v vst,save,lh (data point 6). v vcc will be activated, when v vst achieves the value v vst,vccon (data point 7). the ic is back on regular condition after v vst achieves v busp - v vst_drop (data point 8). with the return - ing v vcc the v 33i output (compare figure 6 confgurable power management ) make a switchover to v vcc if v vcc is in a valid range for 3.3v otherwise the input of the internal v 33i regulator switch to v vst and the output of v 33i regulator switch to v v33i output. and fnally v20 re - covers. the 2 nd case with data point 10 to 14 is like the case be - fore, but now the v vst drop deeper and fnally e981.03 will be reset when v 33i is lower than v 33i , reset, act (data point 14). elmos semiconductor ag data sheet qm-no.: 25ds0046e.03 production data - jan 15, 2015 elmos semiconductor ag reserves the right to change the detail specifcations as may be required to permit improvements in the design of its products. knx / eib transceiver e981.03
20/51 in fgure 10 the four communication sub modes are shown. the mode controlling registers can be modifed through uart or spi commands. for mode controlling registers see registers devmode und cmode . the prioritization is higher with a lower value. save_n t reset_n t i v33i t i busp,max i busp,ss i busp,sspu v vst,vccon v v20,off v vst,save,hl v vst,save,lh v vst,vccoff v reset_n,hl v busp v vst v v33i v vcc i vst i v33i,vcc i v33i,vst softstart phase 2 t t i busp v v20 v i 2 v v33i,reset,act 10 11 1 3 4 5 6 7 8 9 12 13 14 figure 9. undervoltage condition 6.4 communication mode a n a l o g m o de bu s m o n i t o r i n g m o d e bu s y m o d e n o r m a l mo d e b s 1 = 1 b s 0 = 1 c m od = b us m onit or ing c m od = b us y communication mode { o p t i o n a l } a d d r e ss e d m o d e c m od = n or m al figure 10. e981.03 communication mode mode prioritization hard reset 1 star t-up 2 soft reset 3 analog 4 normal 5 bus monitor 5 busy 4 elmos semiconductor ag data sheet qm-no.: 25ds0046e.03 production data - jan 15, 2015 elmos semiconductor ag reserves the right to change the detail specifcations as may be required to permit improvements in the design of its products. knx / eib transceiver e981.03
21/51 activation analog mode is activated if ? no higher prioritize mode is active (e.g. reset, starup) and the baud rate select pins bs0 and bs1 have both high level deactivation analog mode will be left for ? a higher prior mode (e.g. reset) if the activation condition for that modes holds or ? normal mode if any of the baud rate select pins has low level activation monitor mode can be activated if ? no higher prioritize mode is active (e.g. reset, startup, busy) and ? the cmode register has the bus monitor mode value the cmode register can be modifed by ? sending a u_activatebusmon service request via uart or ? writing to the cmode register via spi or uart deactivation bus monitor mode can be left for any higher prioritize mode (e.g. reset) if the activation condition for that modes holds. switching to busy mode is not possible in bus monitor mode. properties ? the data link layer of the uart is in bus monitor mode. only the local l_busmon service is available for the host processor. all l_data host to e981.03 services including l_poll_data service are not avail - able and will be ignored. ? each byte received on the knx / eib is sent to the host as well as illegal control bytes and all acknowl - edge frames. 6.5 analog mode properties ? ic is fully functional (all supplies active) ? host uart interface is switched off. no uart service is available ? bypass from knx transceiver to uart transceiver is active ? host spi interface is active (may be switched off by host processor) comparable to 'medium attachment unit (mau)' knx standard: volume 3 system specifcations: physical layer general 6.6 monitoring mode ? e981.03 is quiet (not sending) on the knx bus. ? writing to the telegram buffers in bus monitoring mode is possible. ? the transmit frame buffer content will not be trans - mitted to the knx bus in bus monitoring mode. ? u_reset.request clears the transmit buffer ready fag (flag ready in register knx_tr_buf_stat). leaving bus monitoring mode without clearing this fag results in transmission of the transmit buffer content on knx bus. ? alarm telegrams can be transmitted even in bus monitor mode. all received telegrams are sent byte-wise from e981.03 to the host. switching to busy mode is not allowed in bus monitor - ing mode. bus monitoring mode will be deactivated on activation of busy mode. it is recommended to activate and deactivate bus mon - itoring mode using uart service requests. activation using direct register access will be described in an ap - plication note. elmos semiconductor ag data sheet qm-no.: 25ds0046e.03 production data - jan 15, 2015 elmos semiconductor ag reserves the right to change the detail specifcations as may be required to permit improvements in the design of its products. knx / eib transceiver e981.03
22/51 activation the normal mode is active if ? no higher prioritized mode is active (e.g. reset, start-up) and ? the cmod register has the normal mode value deactivation the normal mode will be left for ? any higher prior mode (e.g. reset) if the activation condition for that modes holds or ? another cmod controlled mode in case of cmod value change if the host controller is temporarily not able to receive telegrams from the bus (e.g. due to no code execution during fash erase), the busy mode can be estimated to reject frames from the bus with busy acknowledges independently from host acknowledge information in knx busy mode. activation busy mode can be activated if ? no higher prior mode is active (e.g. reset, startup) and ? the cmode register has the busy mode value busy mode activation during active busy mode is ig - nored. the busy mode duration is not prolongated. busy mode activation in active bus monitor mode is not supported. the cmode register can be modifed by ? sending a u_activatebusymode service request via uart or ? writing to the cmode register via spi or uart deactivation busy mode can be left for ? any higher prior mode (e.g. reset) if the activation condition for that modes holds or ? another cmode controlled mode in case of cmode value change 6.7 busy mode ? the cmode register can be modifed by - sending an u_ackinfo or an u_resetbusymode service request via uart or - writing to the cmode register via spi or uart or - internal logic when reaching timeout defned by register busy_reg - after timeout of defned in register busy_reg. properties ? the ic is in full function (all supplies may be switched on) ? knx / eib, uart and spi interfaces are active (de - pendent on their control register contents) but e981.03 rejects following telegrams from the bus with busy acknowledges 1) individually addressed telegrams with their destina - tion address matching the individual address stored in the registers (addressed mode only) 2) all group telegrams including broadcast all other frames will not be acknowledged with busy. all received telegrams are sent byte-wise from e981.03 to the host. remark busy mode activation in active bus monitoring mode is not supported. the ic would switch from bus monitor - ing mode to busy mode but busy acknowledging will be delayed. 6.8 normal mode properties ? the ic is in full function (all supplies may be switched on) ? knx / eib, uart and spi compatible interfaces are active (dependent on their control register con - tents) ? uart is in normal (full) mode as long as uart is not switched off by spi access ? all uart services are available all received telegrams are sent byte-wise from e981.03 to the host. elmos semiconductor ag data sheet qm-no.: 25ds0046e.03 production data - jan 15, 2015 elmos semiconductor ag reserves the right to change the detail specifcations as may be required to permit improvements in the design of its products. knx / eib transceiver e981.03
23/51 6.9 addressed mode each knx / eib device has it's own unique individual ad - dress in a network. the e981.03 can be confgured with an individual node (physical) address. in this mode, the processor load will be reduced by the autonomous knx protocol handling. activation ? after a complete address upload ? activated valid bit in knx_adr_stat register deactivation ? reset / power up sequence ? deactivated valid bit in knx_adr_stat register during any communication mode (but not in analog mode) an alarm sequence can be used to signal improp - er node state to the system via knx / eib bus by send - ing an alarm telegram. activation ? after a complete alarm telegram upload and alarm condition (setvcc pin open or forced to v v33i /2 = v vsetvcc,alarm ) is pending activation ? after upload of a trigger frame to e981.03 and up - load of a trigger telegram mask to e981.03 ? entering busy or normal mode. deactivation ? deactivated buf bit in trigger register. properties wk pin is a tristate pin (tristate push pull) the e981.03 forces in reset / power up sequence wk to ground level. e981.03 applies high level at pin wk after either ? a trigger telegram was received correctly or ? a broadcast telegram was received or ? an individually addressed telegram was received properties ? incoming frames will be analyzed ? frames with a physical address will be answered with an acknowledge automatically, if the stored address matched ? all frames with a group address will be answered automatically with an acknowledge. ? the host can suppress an automatic acknowledge generation 6.10 trigger functionality with address equals node address (optional if con - fgured) ? the generated trigger pulse has a length of t trigger,pw. the received telegram can be read from telegram re - ceive buffer until the next telegram arrives on the knx / eib bus. thus the host processor can get information about trigger telegram contents after restarting the node. attention: to be able to get the trigger message in all conditions use the communication interface uart with 115.2kbd or spi. trigger function is not available in bus monitoring mode and analog mode. 6.11 alarm functionality deactivation ? deactivated buf bit in alarm_stat register properties ? an alarm telegram is send on knx bus ? active reset will be delay transmission, both alarm telegram buffer and alarm state register are not changed the knx / eib to uart receive path remains active dur - ing alarm sequence. elmos semiconductor ag data sheet qm-no.: 25ds0046e.03 production data - jan 15, 2015 elmos semiconductor ag reserves the right to change the detail specifcations as may be required to permit improvements in the design of its products. knx / eib transceiver e981.03
24/51 the general communication between e981.03 and host is realized by using uart services. furthermore the ic can be confgured via spi interface. any service sent from host to e981.03 consists of one or more bytes. the frst byte is the uart control feld which identifes the type of the requested service. the e981.03 can handle the following service requests: 7 data communication 7.1 uart-service host -> uart service name uart control feld remarks / description followed by n bytes hex bin 7 6 5 4 3 2 1 0 u_reset.request 0x01 0000 0001 after receiving a u_reset. request the ic transits to its soft reset state. u_state.request 0x02 0000 0010 the ic answers an u_state. request service by sending its communication state using state.response service. u_activatebusmon 0x05 0000 0101 u_ackinformation 0x10 ... 0x17 0001 0nba n: nack b: busy a: addressed 0: inactive 1: active u_productid.request 0x20 0010 0000 u_activatebusymode 0x21 0010 0001 the service activates the knx busy mode in the e981.03 u_resetbusymode 0x22 0010 0010 the host shall synchronize its receiver before sending the u_resetbusymode. u_mxrstcnt 0x24 0010 0100 number of busy and nack counts (in one byte) - 0..7 times b2 b1 b0 0 0 n2 n1 n0 busy 0 0 nack knx control feld u_activatecrc 0x25 0010 0101 only with baud rates 19.200 or 115.200 table 4. uart service - host to e981.03 6.12 save mode to enlarge the v vcc operation time during low bus voltage supply the e981.03 switches some power devices off. properties ? knx / eib transmitter is switched off ? the save pin is active low ? knx / eib receiver, uart host and spi host interfaces remain active ? v20 is switched off to allow longer vcc active times elmos semiconductor ag data sheet qm-no.: 25ds0046e.03 production data - jan 15, 2015 elmos semiconductor ag reserves the right to change the detail specifcations as may be required to permit improvements in the design of its products. knx / eib transceiver e981.03
25/51 service name uart control feld remarks / description followed by n bytes hex bin 7 6 5 4 3 2 1 0 u_setaddress 0x28 0010 1000 set knx physical address - individual knx address (high byte) - individual knx address (low byte) a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 u_setalarmtelegramm 0x29 0010 1001 knx control feld which is sent in alarm condition f1 f0 r 1 p1 p2 0 0 frame format re - peat fag priority knx control feld u_settriggertelegram 0x2a 0010 1010 knx control feld which is reason for a event detec - tion f1 f0 r 1 p1 p2 0 0 knx control feld u_settriggertelegrammask 0x2b 0010 1011 knx control feld mask make it possible to detect a event with several combi - nations m7 m6 m5 m4 m3 m2 m1 m0 u_readreg.request 0x2e 0010 1110 read access to the e981.03 internal memories - address (high byte) - address (low byte) 0 0 0 0 0 0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 u_writereg 0x2f 0010 1111 write access to the e981.03 internal memories - address (high byte) - address (low byte) - data byte 0 0 0 0 0 0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 u_l_datastart 0x80 1000 0000 begin data telegram up - load with knx control feld f1 f0 r 1 p1 p0 0 0 knx control feld u_l_datacontinue 0x81 ... 0xbe 10xx xxxx upload data byte with in - dex x x: index (1 ... 62) d7 d6 d5 d4 d3 d2 d1 d0 u_l_dataend 0x47 ... 0x7f 01xx xxxx upload check sum with last index x+1 x: last index+1 (7 ... 63) c7 c6 c5 c4 c3 c2 c1 c0 it is calculated as logical not xor function over the individual bits of the preceding bytes of the frame. u_pollingstate 0xe0 ... 0xef 1110 xxxx upload polling state in to the expecting slot x x: slot number (0 ... 14) - polladdrhigh - polladdrlow - state a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 s7 s6 s5 s4 s3 s2 s1 s0 u_l_longdatacontinue 0xc0 0xc1 1100 000x upload data byte with in - dex x(bit 8 .. 0) (1 ... 263) x: msb (bit 8) of index - index x(bit 7 ... 0) - data byte i7 i6 i5 i4 i3 i2 i1 i0 d7 d6 d5 d4 d3 d2 d1 d0 u_l_longdataend 0xd0 0xd1 1101 000x upload check sum with last index x+1 (bit 8 .. 0) (1 ... 264) x: msb (bit 8) of index - index x(bit 7 ... 0) - data byte i7 i6 i5 i4 i3 i2 i1 i0 d7 d6 d5 d4 d3 d2 d1 d0 it is calculated as logical not xor function over the individual bits of the preceding bytes of the frame. an u_state.indication as a result of faulty uart control feld is sent to the host as soon as possible in the follow - ing cases: ? protocol error fag set: undefned uart control feld ? receiver error fag set: time between subsequent bytes of a service longer than the defned timeout elmos semiconductor ag data sheet qm-no.: 25ds0046e.03 production data - jan 15, 2015 elmos semiconductor ag reserves the right to change the detail specifcations as may be required to permit improvements in the design of its products. knx / eib transceiver e981.03
26/51 any service sent from e981.03 to host consists of one or more bytes. the frst byte is the control feld which identi - fes uart service. the e981.03 can handle the following three different uart services: ? knx data link layer services are complete ? immediate acknowledge service include information about sending state ? uart control services are used to send requested information to the host controller or, in case of failures, a state indication 7.2 uart service uart -> host service name uart control feld remarks / description followed by hex bin 7 6 5 4 3 2 1 0 acknowledge (busy and nack) 0x00 0000 0000 the preceding data tele - gram is negative and busy acknowledged by a combi - nation of receiving nodes. 1) reset.indication 0x03 0000 0011 indicate a reset of the e981.03 l_data.confrm (negative) 0x0b 0000 1011 l_data telegram negative confrm: the preceding data tel - egram was either nega - tive acknowledged (either nack or busy) by receiv - ing node(s) or not acknowl - edged at all. acknowledge (nack) 0x0c 0000 1100 the preceding data tele - gram is negative acknowl - edged by any of the receiv - ing nodes. 1) l_data telegram (l_extdata frame) 0x10 0x14 0x18 0x1c 0x30 0x34 0x38 0x3c 0001 0000 0001 0100 0001 1000 0001 1100 0011 0000 0011 0100 0011 1000 0011 1100 first byte (control feld of an frame which is received on knx bus. 3) an extended data frame (l_ extdata) each complete received byte of the frame will be transmitted. (end of frame indication will be a time gap above t uart,ibg,rx = 2.5ms.) the frame length is between 2 and 264 byte. l_data.confrm (positive) 0x8b 1000 1011 l_data telegram positive confrm: the preceding data tel - egram was positive ac - knowledged (ack) by the receiving node l_data telegram (l_data frame) 0x90 0x94 0x98 0x9c 0xb0 0xb4 0xb8 0xbc 1001 0000 1001 0100 1001 1000 1001 1100 1011 0000 1011 0100 1011 1000 1011 1100 first byte (control feld) of an frame which is re - ceived on knx bus. 3) a data frame (l_data) each complete received byte of the frame will be transmitted. (end of frame indication will be a time gap above t uart,ibg,rx = 2.5ms.) the frame length is between 2 and 64 byte. acknowledge (busy) 0xc0 1100 0000 the preceding data tel - egram is busy acknowl - edged by any of the receiv - ing nodes. 1) acknowledge (ack) 0xcc 1100 1100 the preceding data tel - egram is positive acknowl - edged by all of the receiv - ing nodes. 1) table 5. uart service - e981.03 to host elmos semiconductor ag data sheet qm-no.: 25ds0046e.03 production data - jan 15, 2015 elmos semiconductor ag reserves the right to change the detail specifcations as may be required to permit improvements in the design of its products. knx / eib transceiver e981.03
27/51 service name uart control feld remarks / description followed by hex bin 7 6 5 4 3 2 1 0 l_polldata.request 0xf0 1111 0000 e981.03 is poll_master: uploaded l_polldata.re - quest telegram a data frame (l_polldata. request) each complete received byte of the frame will be transmitted. (end of frame indication will be a time gap above t uart,ibg,rx = 2.5ms.) the frame length is 7 byte. e981.03 is poll_slave: a poll_master can also be a poll_slave write host to uart service u_pollingstate with the cor - responding data u_readreg.response 0xf1 1111 0001 answer of u_readreg.re - quest d7 d6 d5 d4 d3 d2 d1 d0 u_productid.response 0xfe 1111 1110 answer of u_productid.request i7 i6 i5 i4 i3 i2 i1 i0 state.response state.indication 0x_7 and 0x_f abcd e111 a: [sc] b: [re] c: [te] d: [pe] e: [tw] answer of - u_state.request - indication of any state chance: [1] activation [0] deactivation see table below 1) note: all acknowledge frames are transmitted to the host in bus monitor mode only 2) each l_data telegram is transmitted completely to the host controller. 3) each correctly received byte is immediately transferred to the host processor. table 6. e981.03 state indication name bit is set in case of sc: slave collision - an other polling slave uses same slot (and has higher "priority") re: receiver error - check-sum error in uploaded telegram - parity error on uart - frame error on uart (stop bit wrong) - timeout violation between received service bytes te: transmitter error - knx transmitter sends "0", knx receiver receives "1" pe: protocol error - illegal control byte in a service of telegram upload - transmit telegram buffer overrun (upload during telegram transmission on knx bus) - u_l_datacontinue service with index 0 or greater than 263 tw: temperature warning - temperature monitor signals too high temperature 7.3 spi logical layer several bytes transferred subsequently during active chip select form a spi access. the frst byte of a spi ac - cess is the command byte. it contains the following in - formation: 1. distinction between read and write 2. decision whether to transmit a xor check-sum or 3. read accesses information about short or long access 4. upper part of address if the xor bit in the command byte is set a check-sum is calculated over the bytes of the access and transferred as last byte in master --> slave and slave --> master di - rections. thus both master and slave have information about potentially incorrect transfer of command, ad - dress and data bytes. in short form of read access the inter byte gap has to be regarded between byte 2 (address) and byte 3 (data). otherwise the transmitted byte may not be correct. elmos semiconductor ag data sheet qm-no.: 25ds0046e.03 production data - jan 15, 2015 elmos semiconductor ag reserves the right to change the detail specifcations as may be required to permit improvements in the design of its products. knx / eib transceiver e981.03
28/51 via spi the host is able to read all addresses in the ranges 0x000 ... 0x27f and 0x300-3ff. write access is allowed in the address range 0x000 ... 0x17f and 0x200 to 0x27f, except: ? uart_stat (0x2a0) ? uart_rx (0x2a3) ? uart_tx (0x2a4) figure 11. spi read accesses figure 12. spi write accesses elmos semiconductor ag data sheet qm-no.: 25ds0046e.03 production data - jan 15, 2015 elmos semiconductor ag reserves the right to change the detail specifcations as may be required to permit improvements in the design of its products. knx / eib transceiver e981.03
29/51 7.4 spi timing figure 13. spi timing 8 monitoring functions for measurement reasons the voltages are scaled to low voltage domain v33i. for scaling factors please read table electrical characteristics section monitoring functions . for error calculations refer following tolerances: divider, adc, v33i supply (tolerance depend on confguration and mode). as described in section 5.5 aout the aout is an analog monitoring pin with a high impedance. possible sources are: ? temperature voltage ? band gap voltage ? bus voltage adc unit converts a confgurable count of analog signals to 8 bit resolution digital numbers. the signal conversion time of a selected channel is typical 5 s at a clock fre - quency of 4 mhz. the input channels are converted in a continuously running conversion cycle. the adc embed - ded system consists of: 8 bit sar adc core ? high and low level reference generator ? conversion channel mux with input buffer ? channel sequence control unit ? result registers 8.1 analog monitoring functions 8.2 digital monitoring functions in e981.03 adc converts ? bus voltage vbusp ? vst ? v20 ? vcc ? vio ? temperature (for details read chapter 8.3 tempera - ture supervision ) elmos semiconductor ag data sheet qm-no.: 25ds0046e.03 production data - jan 15, 2015 elmos semiconductor ag reserves the right to change the detail specifcations as may be required to permit improvements in the design of its products. knx / eib transceiver e981.03
30/51 for measurement reasons the voltages are scaled to low voltage domain v33i. the scaled voltages are converted by the on chip adc. for scaling factor look at chapter electrical functions section monitoring functions . the conversion results can be read by access to the result registers. the vbusp is an average value (t vbusp(av) = 5 ms). adc control cycle consists of two conversion cycles. the bus voltage is converted in the frst conversion cycle of every control cycle. all other analog channels are con - verted in the second slot of the control cycle. the result - ing conversion rate is approximately ? 70 k samples for bus voltage ? 10 .. 20 k samples for all other sources note: from vst supervision an active save_n signal is gener - ated in case of falling supply voltages. this allows the host pro - cessor to stop the application program and to save its data be - fore the reset pin reset_n becomes active. e981.03 elmos semiconductor ag 1 / 1 preliminary information jan. 2012 0 x 397 adc _ vstres 0 x 398 adc _ v 20 res 0 x 399 adc _ vccres 0 x 39 a adc _ viores 0 x 39 d adc _ vbusp _ mean 0 x 39 e adc _ tempres 0 x 3 b 1 bus _ curr _ stat ram a d v 20 v cc v io v busp , mean v temp v bus , current internal v st shift pattern aclk m u x figure 14. digital monitoring functions elmos semiconductor ag data sheet qm-no.: 25ds0046e.03 production data - jan 15, 2015 elmos semiconductor ag reserves the right to change the detail specifcations as may be required to permit improvements in the design of its products. knx / eib transceiver e981.03
31/51 the temperature supervision is necessary for protection in case of high power dissipation in failure cases, for example short circuit of supply outputs. in case of over temperature ? the warning signal otemp for the host controller is generated ? in normal mode a state.indication service is sent to the host controller once at the beginning of over temperature situation in case of further temperature rising power consuming blocks are switched off (shutoff phase): ? no further transmission at knx ( knx transmitter is disabled) in both analog and normal modes 8.3 temperature supervision figure 15. over-temperature scenario ? v20 and vcc supplies are switched off ? save is activated ? reset is activated when vcc is lower than the reset limit C not depending on temperature. when e981.03 temperature is lower than the limit: ? vcc and v20 supplies are switched on again ? save_n is deactivated ? knx transmitter is enabled elmos semiconductor ag data sheet qm-no.: 25ds0046e.03 production data - jan 15, 2015 elmos semiconductor ag reserves the right to change the detail specifcations as may be required to permit improvements in the design of its products. knx / eib transceiver e981.03
32/51 9 e981.03 security functions the e981.03 has two security functions featuring an external digital interface. 1) may be written by the host during a l_polldata.request frame. 2) writing to these addresses is not allowed 3) only allowed access to the named registers, see table below (register table). save in case of an invalid vst voltage, the e981.03 activates the save mode to expand an active vcc time. the save pin gives this status of the save mode to an external device (host processor). otemp the temperature supervision is necessary for protection in case of higher power dissipation in failure cases, for example short circuit of supply outputs. the otemp pin gives an over-temperature warning 10 ram and register table 10.1 ram table address bytes content app. note 0x000 ... 0x107 264 transmit frame buffer 0x108 ... 0x109 2 individual knx address of the knx /eib node 0x10a ... 0x10b 2 polling address 1) 0x10c 1 polling slot 1) 0x10d 1 polling data 1) 0x10e ... 0x10f 2 reserved for e981.03 internal use 2) 0x110 ... 0x128 25 alarm telegram buffer 0x129 ... 0x12f 7 reserved for e981.03 internal use 2) 0x130 ... 0x148 25 trigger telegram buffer 0x149 ... 0x14f 7 reserved for e981.03 internal use 2) 0x150 ... 0x168 25 trigger mask buffer 0x169 ... 0x16a 2 length of alarm telegram 0x16b ... 0x16c 2 length of trigger telegram 0x16d ... 0x1bf 82 reserved for e981.03 internal use 2) 0x1c0 ... 0x1ff 64 received frame buffer 2) 0x200 ... 0x2ff 256 registers table 3) 0x300 ... 0x3ff 256 registers table 2) 3) register name address description app. note cmode 0x200 communication mode reset_ctrl 0x201 reset control register busy_reg 0x202 busy mode register spi_ctrl 0x205 spi control register spi_pins 0x206 spi pin access uart_ctrl 0x208 uart control register clk_ctrl 0x209 host clock control register clk_fac0 0x20a lower 8 bit of the clock divider register clk_fac1 0x20b upper 8 bit of the clock divider register ps_ctrl 0x20e power supply control register table 7. ram address ranges table 8. register table 10.2 register table elmos semiconductor ag data sheet qm-no.: 25ds0046e.03 production data - jan 15, 2015 elmos semiconductor ag reserves the right to change the detail specifcations as may be required to permit improvements in the design of its products. knx / eib transceiver e981.03
33/51 back to table 8 register table register name address description res_source 0x302 binary coded reset source register name address description app. note max_bus_curr 0x20f set the maximum dc bus current current_slope 0x210 set up the maximum bus current slope aout_ctrl 0x211 aout control register aout_src 0x212 aout source select register alarm_stat 0x213 alarm status register trigger 0x214 trigger register knx_tr_buf_stat 0x215 status of the transmit telegram buffer knx_ adr_stat 0x216 status of the address max_rst_cnt 0x217 number of retries in case of not acknowledge and busy knx_tx_len1 0x218 length of the frame in the transmit buffer (bits 8) knx_tx_len0 0x219 length of the frame in the transmit buffer (bits 7 ... 0) ack_host 0x21a acknowledge information from host poll_conf 0x21b status of a polling slave uart_stat 0x2a0 uart status register uart_rx 0x2a3 previous received byte uart_tx 0x2a4 uart transmitter data register devmode 0x300 active device mode res_source 0x302 binary coded reset source pins 0x306 mode control and baud rate select pin values spi_stat 0x310 spi status register prod_id 0x371 product id (read only) adc_vstres 0x397 adc result for the (scaled) voltage on vst adc_v20res 0x398 adc result for the (scaled) voltage on v20 adc_vccres 0x399 adc result for the (scaled) voltage on pin vcc adc_viores 0x39a adc result for the (scaled) voltage on vio adc_vbusp_mean 0x39d mean value for vbusp voltage adc_tempres 0x39e adc result temperature scan bus_curr_stat 0x3b0 actual value of dc bus current ps_stat 0x3bf power supply status register ack_knxic 0x3e9 acknowledge information from e981.03 res_source msb lsb content - - - - - src2 src1 src0 hard reset value 0 0 0 0 0 0 0 0 soft reset value value of reset source access r 1) r 1) r 1) r 1) r 1) r 1) r 1) r 1) bit description src : binary coded reset source (see following table for valid values, reset value is startup reset value) table 9. reset register table 10. binary coded reset source 1) access via uart service and spi possible. in case of hard reset the register is reset to the hard reset value. elmos semiconductor ag data sheet qm-no.: 25ds0046e.03 production data - jan 15, 2015 elmos semiconductor ag reserves the right to change the detail specifcations as may be required to permit improvements in the design of its products. knx / eib transceiver e981.03
34/51 res_source value reset source 0x00 start-up reset (this is the only reset source that corresponds to register hard reset values) 0x01 the previous reset was initiated by an externally driven active reset 0x02 the previous reset was initiated by a reset.request service 0x03 the previous reset was initiated by a write access to the reset_ctrl register 0x04 e981.03 intern watchdog 0x05 the previous reset was initiated by a low vcc 0x07 e981.03 internal error table 11. reset source register name address description busy_reg 0x202 busy mode register register name address description devmode 0x300 active device mode cmode 0x200 communication mode prod_id 0x371 ic product id (read only) pins 0x306 mode control and baud rate select pin values table 12. busy timeout register table 15. device mode registers busy_reg msb lsb content t7 t6 t5 t4 t3 t2 t1 t0 hard reset value 0 0 0 1 1 0 1 0 soft reset value 0 0 0 1 1 0 1 0 access r/w 1) r/w 1) r/w 1) r/w 1) r/w 1) r/w 1) r/w 1) r/w 1) devmode msb lsb content m7 m6 m5 m4 m3 m2 m1 m0 hard reset value 0 0 0 0 0 0 0 0 soft reset value 0 0 0 0 0 0 1 0 access r 1) r 1) r 1) r 1) r 1) r 1) r 1) r 1) bit description this register holds the value of the currently active mode. this mode may differ from the communication mode selected by the cmode register for several reasons. especially dur - ing mode changes the devmode register refects the currently active mode. table 13. busy_reg table 16. active device mode back to table 8 register table back to table 8 register table 1) access via uart service and spi possible. in case of hard or soft reset the register is reset to the hard reset value or soft reset value respectively. timebase is 4 ms per digit. 1) access via uart service and spi possible. in case of hard or soft reset the register is reset to the hard reset value or soft reset value respectively. register cmode is used for ic control and is intended to be written by host controller. register devmode refects the state of the ic. busy_reg value timeout value 255 1.02 s 175 0.7 s 26 (default) 0.1 s 0 0 s table 14. timeout examples elmos semiconductor ag data sheet qm-no.: 25ds0046e.03 production data - jan 15, 2015 elmos semiconductor ag reserves the right to change the detail specifcations as may be required to permit improvements in the design of its products. knx / eib transceiver e981.03
35/51 1) access via uart service and spi possible. in case of hard or soft reset the register is reset to the hard reset value or soft reset value respectively. 1) access via uart service and spi possible. in case of hard reset the register is reset to the hard reset value. 1) access via uart service and spi possible. mode priority register cmode register devmode remarks hard reset 1 don't care 0x00 reset state is active if internal power supply is down star t-up 3 don't care 0x01 soft reset 4 don't care 0x02 analog 5 don't care 0x03 normal 5 0x04 0x04 0x04 is the reset value of register cmode normal mode is active in case of cmode values that do not defne an other communication mode. bus monitor 5 0x05 0x05 busy 4 0x06 0x06 table 18. e981.03 mode register values cmode msb lsb content - - - - - cm2 cm1 cm0 hard reset value 0 0 0 0 0 1 0 0 soft reset value - - - - - 1 0 0 access r 1) r 1) r 1) r 1) r 1) r/w 1) r/w 1) r/w 1) prod_id msb lsb content id7 id6 id5 id4 id3 id2 id1 id0 hard reset value 0 0 0 0 0 1 0 0 soft reset value never changed access r 1) r 1) r 1) r 1) r 1) r 1) r 1) r 1) bit description product id will be changed in case of feature change. pins msb lsb content setvcc bs1 bs0 alarm 0 wk reset save access r r r r r r r r bit description setvcc : this bits refects the value of the setvcc pin information bs1 : this bits refects the value of the bs1 pin bs0 : this bits refects the value of the bs0 pin alarm : this bits refects the value of the alarm condition (setvcc=v setvcc,alarm ) wk : this bits refects the value of the wk pin reset : this bits refects the value of the reset pin save : this bits refects the value of the save pin back to table 8 register table back to table 8 register table back to table 8 register table the state of several pins are accessible via register address pins. the read value changes with pin voltages with - out respect to ic state. table 17. communication mode table 19. ic product id (read only) table 20. mode control and baud rate select pin values elmos semiconductor ag data sheet qm-no.: 25ds0046e.03 production data - jan 15, 2015 elmos semiconductor ag reserves the right to change the detail specifcations as may be required to permit improvements in the design of its products. knx / eib transceiver e981.03
36/51 trigger msb lsb content - - - - event en_out mask_buf buf hard reset value 0 0 0 0 0 1 0 0 soft reset value - - - - - 1 0 0 access r 1) r 1) r 1) r 1) r/w 1) r/w 1) r/w 1) r/w 1) bit description event : "1": a trigger event was detected "0": no trigger event detected the event bit is initially cleared. if the ic receives a triggering telegram on knx bus it ac - knowledges this telegram by sending a busy acknowledge on knx bus and sets the event bit. any further incoming triggering telegram will not be busy acknowledged by the ic as long as the host does not clear the event bit by writing a "0". acknowledge generation based on auto address mode is not affected by the event bit state. en_out : "1": enable output stage (pull down disabled) "0": disable output stage (output tri-state, pull down enabled) mask_buf : "1": the trigger mask buffer was written completely "0": the trigger buffer was not written completely yet buf : "1": the trigger buffer was written completely "0": the trigger buffer was not written completely yet bits mask_buf and buf are set by the e981.03 after successful upload using host uart interface. they may be written by the host directly. alarm_stat msb lsb content - - - - - pend buf sent hard reset value 0 0 0 0 0 0 0 0 back to table 8 register table back to table 8 register table table 22. trigger register table 24. alarm status register power supply registers 1) access via uart service and spi possible. in case of hard or soft reset the register is reset to the hard reset value or soft reset value respectively. register name address description alarm_stat 0x213 alarm status register alarm_buf 0x110... 0x128 25 byte alarm telegram buffer alarm_len1 0x169 length of alarm telegram (high byte) alarm_len0 0x16a length of alarm telegram (low byte) table 23. alarm state register the alarm state register is used to signal the state of the alarm functionality and to control sending of the alarm telegram. reading the register is allowed any time using any interface. writing to the register is only recommended to clear the sent bit and allow resending of the alarm telegram. a successful alarm telegram transmission is con - frmed to the host by sending a l_data.confrm service on host uart interface. register name address description trigger 0x214 wake-up register trigger_buf 0x130 ... 0x148 25 byte trigger telegram buffer trigger_mask 0x150 ... 0x168 25 byte trigger telegram mask buffer trigger_len1 0x16b length of trigger telegram (high byte) trigger_len0 0x16c length of trigger telegram (low byte) table 21. overview trigger register elmos semiconductor ag data sheet qm-no.: 25ds0046e.03 production data - jan 15, 2015 elmos semiconductor ag reserves the right to change the detail specifcations as may be required to permit improvements in the design of its products. knx / eib transceiver e981.03
37/51 1) access via uart service and spi possible. for write access read the remarks of every bit carefully. in case of hard reset the register is reset to the hard reset value. ps_ctrl msb lsb content vio_sw - vcc_on1 1) vcc_on0 1) - - v20_on1 1) v20_on0 1) hard reset value 0 0 1 1 0 0 1 1 soft reset value 0 - 1 1 - - 1 1 external access r/w 2) r r/w 2) r/w 2) r r r/w 2) r/w 2) bit description vcc_on : 00: vcc is to switch off 1) 01,10,11: v cc is to switch on the bits do not refect the state of the v cc supply. the actual state is refected by ps_stat register. v20_on : "00": v 20 is to switch off 1) 01,10,11: v 20 is to switch on the bits do not refect the state of the v 20 supply. the actual state is refected by ps_stat register. vio_sw: when vcc = 5 v and vio = 3.3 v: write 1 to vio_sw bit to reduce power consumption of e981.03. in all other cases this bit has no effect. back to table 8 register table table 26. power supply control register 1) the bits vcc_on and v20_on are doubled for safety reasons. vcc and v20 supplies are switched off only if both on bits have value "0". otherwise the supply is switched on and the on bits are set to value "1" by the e981.03 itself. 2) access via uart service and spi possible. in case of hard or soft reset the register is reset to the hard reset value or soft reset value respectively. register name address description ps_ctrl 0x20e power supply control register ps_stat 0x3bf power supply status register table 25. power supply registers alarm_stat msb lsb soft reset value - - - - - - - - external access r 1) r 1) r 1) r 1) r 1) r/(w) 1) r/w 1) r/w 1) bit description pend : "1": an alarm transmission is either pending, under transmission or sent (e.g. in case of alarm pin activation during transmission of a "normal" telegram) "0": no alarm is pending or sent writing to the register using uart u_writereg service clears the pend bit independent of the value that is written to that bit. writing using spi shall not change the value of the pend bit which is not controlled by the e981.03 but is in the responsibility of the host controller. buf : "1": the alarm buffer was written completely "0": the alarm buffer was not written completely yet the bit is set by the e981.03 after successful upload using host uart interface services. it may be written by the host directly to activate alarm functionality without using upload procedure via host uart interface or after uploading a alarm telegramm by spi. the alarm telegram buffer is not checked for correctness in this case. sent : "1": an alarm telegram was sent "0": no alarm telegram was sent the bit is set after sending of an alarm telegram. it can be reset by the host processor by writing a "0". the host should never write an 1 to the sent bit. if the bit sent is set no alarm telegram is transmitted regardless of the alarm condition. an ongoing alarm telegram transmission on eib bus (states alarmtelegramwait and alarmtelegramtransmit) is not interrupted by writing a 0 to the sent bit. a reading by uart interface delete this bit. a spi read do not delete this and the user have to do this. elmos semiconductor ag data sheet qm-no.: 25ds0046e.03 production data - jan 15, 2015 elmos semiconductor ag reserves the right to change the detail specifcations as may be required to permit improvements in the design of its products. knx / eib transceiver e981.03
38/51 ps_stat msb lsb content - - - - - - vcc_on v20_on hard reset value 0 0 0 0 0 0 0 0 soft reset value - (not reset) access r 1) r 1) r 1) r 1) r 1) r 1) r 1) r 1) bit description vcc_on : this bit represents the actual state of the vcc supply. "1": v cc is switched on. "0": v cc is switched off. v20_on : this bit represents the actual state of the v20 supply. "1": v 20 is switched on. "0": v 20 is switched off. max_bus_curr msb lsb content maxcurr7 maxcurr6 - - - - - - hard reset value 1 1 0 0 0 0 0 0 soft reset value 1 1 - - - - - - access r/w 1) r/w 1) r 1) r 1) r 1) r 1) r 1) r 1) bit description maxcurr : maximum dc bus current selection bus_curr_stat msb lsb content curr7 curr6 curr5 curr4 curr3 curr2 curr1 curr0 hard reset value 0 0 0 0 0 0 0 0 soft reset value - (not reset) access r 1) r 1) r 1) r 1) r 1) r 1) r 1) r 1) back to table 8 register table back to table 8 register table back to table 8 register table table 27. power supply status register table 29. maximum dc bus current table 31. actual value of dc bus current register name address description max_bus_curr 0x20f set the maximum dc bus current bus_curr_stat 0x3b0 actual adc value of dc bus current current_slope 0x210 set up the maximum bus current slope table 28. bus current source registers 1) for write access read the remarks of every bit carefully. in case of hard or soft reset the register is reset to the hard reset value or soft reset value respectively. 1) access via uart service and spi possible. in case of hard reset the register is reset to the hard reset value. 1) access via uart service and spi possible. in case of hard reset the register is reset to the hard reset value. maxcurr7 maxcurr6 maximum dc bus current min typ max 1 0 11.4 ma 12 ma 12.6 ma 1 1 17.1 ma 18 ma 18.9 ma 0 0 22.8 ma 24 ma 25.2 ma 0 1 28.5 ma 30 ma 31.5 ma table 30. maximum dc bus current selection in case vcc supply is switched off and either register ps_ctrl access or u_reset.request uart service are used to switch vcc on the following will occur: ? vcc is switched on ? vcc is below its reset limit ? reset will be activated ? soft reset will be performed remark: as a result the e981.03 will restart with soft reset in these cases. especially v20 will be switched on too. elmos semiconductor ag data sheet qm-no.: 25ds0046e.03 production data - jan 15, 2015 elmos semiconductor ag reserves the right to change the detail specifcations as may be required to permit improvements in the design of its products. knx / eib transceiver e981.03
39/51 current_slope msb lsb content - - - - - - sl1 sl0 hard reset value 0 0 0 0 0 0 0 1 soft reset value - - - - - - 0 1 access r r r r r r r/w 1) r/w 1) bit description see following table for sl values. back to table 8 register table table 32. set up the maximum bus current slope 1) access via uart service and spi possible. for write access read the remarks of every bit carefully. in case of hard or soft reset the register is reset to the hard reset value or soft reset value respectively. clk_ctrl msb lsb content - - - - - ext_ q - enq hard reset value 0 0 0 0 0 0 0 1 soft reset value - - - - - 0 - 1 access r r r r r w 1) r r/w 1) bit description ext_ q : ?1: xtal is used as clock input from external clock source, extal is left open and internal capacitors are disconnected ?0: a quartz is connected to xtal and extal enq : ?1: crystal or clock enabled ?0: crystal or clock disabled and xtal grounded useful e.g. for analog mode clk_fac0 msb lsb content f7 f6 f5 f4 f3 f2 f1 f0 hard reset value 0 0 1 1 0 0 0 0 soft reset value 0 0 1 1 0 0 0 0 access r/w 1) r/w 1) r/w 1) r/w 1) r/w 1) r/w 1) r/w 1) r/w 1) back to table 8 register table back to table 8 register table table 35. host clock control register table 36. clock divider register (low part) register name address description clk_ctrl 0x209 host clock control register clk_fac0 0x20a lower 8 bit of the clock divider register clk_fac1 0x20b upper 8 bit of the clock divider register sl1 sl0 slope limitation mode, ma/ms 0 0 0.25 0 1 0.5 (default) 1 0 1.25 1 1 2.5 table 34. clock registersset up the maximum bus current slope table 33. bus current slope selection values 1) for write access read the remarks of every bit carefully. in case of soft and hard reset the state machine writes mentioned values. 1) access via uart service and spi possible. for write access read the remarks of every bit carefully. in case of hard or soft reset the register is reset to the hard reset value or soft reset value respectively. elmos semiconductor ag data sheet qm-no.: 25ds0046e.03 production data - jan 15, 2015 elmos semiconductor ag reserves the right to change the detail specifcations as may be required to permit improvements in the design of its products. knx / eib transceiver e981.03
40/51 the clock divider has a total reset value of 58.254. when using other quartz frequencies than 7.3728 mhz the value has to be changed to d q = f quartz / 126.76532 hz - 1 before changing the clock divider register values the timing unit of the e981.03 runs with the accuracy of the rc oscillator. communication using the host uart interface has to take that accuracy into account. speci - fed uart and knx communication parameter ranges are not guaranteed before adaption of the clock divider register. the pll has a tolerance of approximately 10% to input frequency for locking. as a result quartz frequencies in the range between f quartz, nom C 10% and f quartz, nom + 10% may be regarded as the nominal quartz frequen - cy resulting in incorrect timing at the knx and uart interfaces. it is highly recommended not to use quartz frequencies in that range or to change the clk_fac reg - isters using spi after each reset of the e981.03. individual node address each knx device has a unique individual address in a network. the individual address is a 2 byte value that consists of an 8 bit subnetwork address and an 8 bit device address. the device address may have any value between 0 and 255. the individual node address can be uploaded to the e981.03 from host using ? service request u_setaddress on uart interface (see chapter 7.1 uart-service host -> uart ) or writ - ing to the appropriate ram addresses (see chapter 7.3 spi logical layer for details) and validate the ad - dress by writing to the knx_adr_stat register. after upload address evaluation in e981.03 is activated. after both hard and soft reset the address evaluation of e981.03 is deactivated. the device address shall be unique within a sub-net - work. the device address in e981.03 is not initialized to a defned value. figure 16. knx individual address clk_fac1 msb lsb content f7 f6 f5 f4 f3 f2 f1 f0 hard reset value 1 1 1 0 0 0 1 1 soft reset value 1 1 1 0 0 0 1 1 access r/w 1) r/w 1) r/w 1) r/w 1) r/w 1) r/w 1) r/w 1) r/w 1) back to table 8 register table table 37. clock divider register (high part) 1) access via uart service and spi possible. for write access read the remarks of every bit carefully. in case of hard or soft reset the register is reset to the hard reset value or soft reset value respectively. a 3 a 2 a 1 a 0 l 3 l 2 l 1 l 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 k n x s ubn e t a dre s s h i g h b y t e ( 0 x 1 0 8 ) m s b l s b a r e a a d r e s s l in e a d r e s s d e v i c e a d r e s s k n x s ubn e t a dre s s l o w b y t e ( 0 x 1 0 9 ) elmos semiconductor ag data sheet qm-no.: 25ds0046e.03 production data - jan 15, 2015 elmos semiconductor ag reserves the right to change the detail specifcations as may be required to permit improvements in the design of its products. knx / eib transceiver e981.03
41/51 register name address description knx_ adr_stat 0x216 status of the address knx_adr_high 0x108 knx subnet adress high byte knx_adr_low 0x109 knx subnet adress low byte register name address description max_rst_cnt 0x217 number of retries in case of not acknowledge and busy knx_tr_buf_stat 0x215 status of the transmit telegram buffer knx_tx_len1 0x218 length of the frame in the transmit buffer (bit 8) 1) knx_tx_len0 0x219 length of the frame in the transmit buffer (bits 7 ... 0) 1) knx_tr_buf 0x000 0x107 264 byte transmit buffer knx_rc_buf 0x1c0 0x1ff 64 byte receiving frame buffer table 38. knx address register table 40. telegram transmission register knx_adr_stat msb lsb content - - - - - - - valid hard reset value 0 0 0 0 0 0 0 0 soft reset value - - - - - - - 0 access r r r r r r r r/w 1) bit description valid : "1": the stored address is valid "0": the stored address is invalid the bit is set by the host by writing to the register or by using u_setaddress service re - quest it is reset. if the address is confgured by spi the user have to set this bit too. - by the host by writing to the register and - during soft reset table 39. status of the knx address back to table 8 register table 1) the length of the frame gives the number of bytes stored in the frame transmit buffer including all frame overhead. 1) access via uart service and spi possible. in case of hard or soft reset the register is reset to the hard reset value or soft reset value respectively. 1) access via uart service and spi possible. in case of hard or soft reset the register is reset to the hard reset value or soft reset value respectively. max_rst_cnt msb lsb content - busy2 busy1 busy0 - nack2 nack1 nack0 hard reset value 0 0 1 1 0 0 1 1 soft reset value - 0 1 1 - 0 1 1 access r r/w 1) r/w 1) r/w 1) r r/w 1) r/w 1) r/w 1) bit description ack : number of retries in case of not acknowledge (either nack on no ack frame) busy : number of retries in case of busy (busy or simultaneously busy and nack) table 41. max_rst_cnt back to table 8 register table elmos semiconductor ag data sheet qm-no.: 25ds0046e.03 production data - jan 15, 2015 elmos semiconductor ag reserves the right to change the detail specifcations as may be required to permit improvements in the design of its products. knx / eib transceiver e981.03
42/51 register name address description ack_host 0x21a acknowledge information from host ack_ knx ic 0x3e9 acknowledge information from e981.03 table 45. acknowledge state register knx_tr_buf_ stat msb lsb content - - - - - - - ready hard reset value 0 0 0 0 0 0 0 0 soft reset value - - - - - - - 0 access r r r r r r r r/w 1) bit description ready : "1": the ram buffer is ready for transmission "0": the ram buffer is not yet ready for transmission the bit is set by either the host processor or internal logic and reset after successful trans - mission. a manual write is only necessary if the frame is uploaded by spi knx_tx_len1 msb lsb content - - - - - - - len8 hard reset value 0 0 0 0 0 0 0 0 soft reset value - - - - - - - 0 access r r r r r r r r/w 1) knx_tx_len0 msb lsb content len7 len6 len5 len4 len3 len2 len1 len0 hard reset value 0 0 0 0 0 0 0 0 soft reset value 0 0 0 0 0 0 0 0 access r/w 1) r/w 1) r/w 1) r/w 1) r/w 1) r/w 1) r/w 1) r/w 1) table 42. status of the transmit telegram buffer table 43. length of the frame in the transmit buffer (bit 8) table 44. length of the frame in the transmit buffer (bits 7 ... 0) back to table 8 register table back to table 8 register table back to table 8 register table 1) access via uart service and spi possible. for write access read the remarks of every bit carefully. in case of hard or soft reset the register is reset to the hard reset value or soft reset value respectively. 1) access via uart service and spi possible. if a frame is uploaded by spi the host controller have to set the len bits. in case of hard or soft reset the register is reset to the hard reset value or soft reset value respectively. 1) access via uart service and spi possible. if a frame is uploaded by spi the host controller have to set the len bits. in case of hard or soft reset the register is reset to the hard reset value or soft reset value respectively. ack_host msb lsb content - - - - rx_ack nack busy adr hard reset value 0 0 0 0 0 0 0 0 soft reset value - - - - - - - - external access r r r r r/w 1) r/w 1) r/w 1) r/w 1) bit description rx_ack :?1": acknowledge information from host for frame currently received "0": no acknowledge information from host for frame currently received bit is set by host access via spi or uart and reset by internal logic at start of a frame on knx line. nack : not acknowledge fag busy : busy fag adr : addressed fag all fags are reset by the e981.03 at the beginning of a received frame. table 46. acknowledge information from host back to table 8 register table 1) access via uart service and spi possible. if a frame is uploaded by spi the host controller have to set the len bits. in case of hard reset the register is reset to the hard reset value. elmos semiconductor ag data sheet qm-no.: 25ds0046e.03 production data - jan 15, 2015 elmos semiconductor ag reserves the right to change the detail specifcations as may be required to permit improvements in the design of its products. knx / eib transceiver e981.03
43/51 ack_knxic msb lsb content - - - - - nack busy adr hard reset value 0 0 0 0 0 0 0 0 soft reset value - - - - - - - - access r r r r r r 1) r 1) r 1) bit description nack : not acknowledge fag busy : busy fag adr : addressed fag all fags are reset by the e981.03 at the beginning of a received frame. poll_conf msb lsb content - - - - - - - valid hard reset value 0 0 0 0 0 0 0 0 soft reset value - - - - - - - 0 access r r r r r r r r/w 1) bit description valid : "1": the data in the polling slave ram area is valid for transmission "0": the data in the polling slave ram area is invalid this bit is set by either the u_pollingstate uart service request or direct writing to the register by the host. if the confguration is don by spi the user have to set this bit too. it is reset by the e981.03 at the begin of a l_polldata.request frame reception on knx bus ( knx control feld 0xf0 was received). table 47. acknowledge information used by e981.03 for previous received telegram table 49. status of a polling slave back to table 8 register table back to table 8 register table 1) access via uart service and spi possible. in case of hard reset the register is reset to the hard reset value. 1) access via uart service and spi possible. in case of hard or soft reset the register is reset to the hard reset value or soft reset value respectively. pollconf register poll_conf is completely handled by e981.03 when using host uart interface for communication. when using host spi interface the host has to handle poll_conf register itself. register name address description poll_conf 0x21b status of a polling slave poll_adr_high 0x10a high byte poll_adr_low 0x10b low byte poll_slot 0x10c polling slot poll_data 0x10d polling data table 48. polling slave register the uart_ctrl register is used to control properties of the uart by host processor software. it is not modifed by the e981.03. the uart_stat register is used to signal uart state to the host processor software. the host is not allowed to modify the uart_stat register. register name address description uart_ctrl 0x208 uart control register uart_stat 0x2a0 uart status register table 50. uart registers elmos semiconductor ag data sheet qm-no.: 25ds0046e.03 production data - jan 15, 2015 elmos semiconductor ag reserves the right to change the detail specifcations as may be required to permit improvements in the design of its products. knx / eib transceiver e981.03
44/51 uart_stat msb lsb content - - - - - - - on hard reset value 0 0 0 0 0 0 0 0 soft reset value - (not reset) access r r r r r r r r 1) bit description on : "1": the uart interface is currently on "0": the uart interface is currently off. this may be because of analog mode activation or because of a host write access to the uart_ctrl register uart_ctrl msb lsb content - - - txdel crc - on1 on0 hard reset value 0 0 0 0 0 0 1 1 soft reset value - - - 0 0 - 1 1 access r r r r/w 1) r/w 1) r r/w 1) r/w 1) bit description txdel : "1": activate constant transmission delay between end of uart service and start of trans - mission on knx bus "0": transmission delay between end of uart service and start of transmission on eib bus is variable (faster) crc : "1": the uart crc is enabled (not available in analog mode and not at 9.6kbd) "0": the uart crc is disabled on1 : on0 : "-1" or "1-": the uart is switched on "00": the uart is switched off table 52. uart status register table 51. uart control register back to table 8 register table back to table 8 register table 1. the bit on is doubled for safety reasons. uart interface is switched off only if both on bits have value "0". otherwise uart interface is switched on and the on bits are set to value "1" by the e981.03 itself. 2. bits on1 and on0 can not be modifed using u_writereg service request. use spi to switch uart on and off. bits txdel and crc can be modifed using either u_writereg service request or spi. 3. bit crc is used to activate crc calculation on uart to host communication. crc is not used in case of knx bus monitor mode or 9.6 k baud uart speed, independent on the value of the crc bit of register uart_ctrl. uart byte receiver the parity bit of every received byte from the host will be checked by the e981.03. errors will be reported to the host controller by sending a state.indication service with receiver error fag set to the host as soon as possible. the uart receiver accepts frames up to a maximum baud rate deviation of 3%. the signals can be transmitted without a break. register name address description uart_rx 0x2a3 previous received byte table 53. uart receiver registers 1) access via uart service and spi possible. in case of hard or soft reset the register is reset to the hard reset value or soft reset value respectively. 1) access via uart service and spi possible. in case of hard reset the register is reset to the hard reset value. elmos semiconductor ag data sheet qm-no.: 25ds0046e.03 production data - jan 15, 2015 elmos semiconductor ag reserves the right to change the detail specifcations as may be required to permit improvements in the design of its products. knx / eib transceiver e981.03
45/51 register name address description uart_tx 0x2a4 uart transmitter data register register name address description spi_ctrl 0x205 spi control register spi_stat 0x310 spi status register spi_pins 0x206 spi pin access table 55. uart transmitter registers table 57. spi registers uart_rx msb lsb content d7 d6 d5 d4 d3 d2 d1 d0 hard reset value 0 0 0 0 0 0 0 0 soft reset value -(not reset) access r 1) r 1) r 1) r 1) r 1) r 1) r 1) r 1) uart_tx msb lsb content d7 d6 d5 d4 d3 d2 d1 d0 hard reset value 0 0 0 0 0 0 0 0 soft reset value -(not reset) access r 1) r 1) r 1) r 1) r 1) r 1) r 1) r 1) table 54. previous received byte table 56. uart transmitter data register back to table 8 register table back to table 8 register table back to table 8 register table back to table 8 register table uart byte transmitter txd idle-level in any other mode but knx analog mode is "1". the uart transmitter has a baud rate deviation of less than 1% during byte frame transmission. subsequent bytes may be transmitted without a break. spi_ctrl msb lsb content - - - - - - on1 on0 hard reset value 0 0 0 0 0 0 1 1 soft reset value - - - - - - 1 1 access r r r r r r r/w 1) r/w 1) bit description on1 : on0 : "-1" or "1-": the spi is switched on "00": the spi is switched off spi_stat msb lsb content - - - - - - - xerr hard reset value 0 0 0 0 0 0 0 0 soft reset value - (not reset) access r r r r r r r r 1) bit description xerr : xor error detected table 58. spi control register table 59. spi status register 1) access via uart service and spi possible. in case of hard reset the register is reset to the hard reset value. 1) access via uart service and spi possible. in case of hard reset the register is reset to the hard reset value. 1) access via uart service and spi possible. in case of hard or soft reset the register is reset to the hard reset value or soft reset value respectively. 1) access via uart service and spi possible. in case of hard reset the register is reset to the hard reset value. elmos semiconductor ag data sheet qm-no.: 25ds0046e.03 production data - jan 15, 2015 elmos semiconductor ag reserves the right to change the detail specifcations as may be required to permit improvements in the design of its products. knx / eib transceiver e981.03
46/51 register name address description reset_ctrl 0x201 reset_ctrl control register table 61. reset_ctrl back to table 8 register table back to table 8 register table register spi_pins is used for spi pin value accesses. bits scs and sck refect the state of ic pins in any case of op - eration mode. when spi is switched off (bits on1 and on0 of register spi_ctrl are both ?0) mosi and miso are used as gen - eral purpose input / output of the e981.03 that can be controlled by host processor. pins scs and sck can be used as general purpose input pin. reset_ctrl msb lsb content - - - - - - - rst hard reset value 0 0 0 0 0 0 0 0 soft reset value - - - - - - - 0 access r r r r r r r r/w 1) bit description rst : writing a 1 to bit rst results in a transition to soft reset state. writing to the reset_ctrl register is the way to initiate a soft reset via either host spi or host uart interfaces. spi_pins msb lsb content - - mosien misoen miso mosi scsn sck hard reset value register bits refect always the state of the physical pins defning reset values makes no sense soft reset value spi switched on 0 0 0 1 pin values spi switched off access r r r/w 1) r/w 1) r/w 1) r/w 1) r 1) r 1) bit description mosien : this bit set the pin direction 0 means high ohmic input 1 mean output. misoen : this bit set the pin direction 0 means high ohmic input 1 mean output. (enable for tri-state output) miso : if the pin is used as a input this bit refects the input state and if the pin is used as a output the user write the output level. mosi : if the pin is used as a input this bit refects the input state and if the pin is used as a output the user write the output level. scsn : this bit refects the input state of the scs pin sck : this bit refects the input state of the sck pin table 62. reset_ctrl control register table 60. spi pin access 1) access via uart service and spi possible. 1) access via uart service and spi possible. in case of hard or soft reset the register is reset to the hard reset value or soft reset value respectively. elmos semiconductor ag data sheet qm-no.: 25ds0046e.03 production data - jan 15, 2015 elmos semiconductor ag reserves the right to change the detail specifcations as may be required to permit improvements in the design of its products. knx / eib transceiver e981.03
47/51 1) access via uart service and spi possible. in case of hard reset the register is reset to the hard reset value. 1) access via uart service and spi possible. in case of hard reset the register is reset to the hard reset value. 1) access via uart service and spi possible. in case of hard reset the register is reset to the hard reset value. 1) access via uart service and spi possible. in case of hard reset the register is reset to the hard reset value. register name address description adc_vbusp_mean 0x39d mean value for v busp voltage 1 lsb=v busp,mean *scale vbusp,adc /v33i +- 5% adc_vstres 0x397 adc result for the (scaled) voltage on v st 1 lsb=v vst *scale vst,adc /v33i +- 5% adc_v20res 0x398 adc result for the (scaled) voltage on v 20 1 lsb=v 20 *scale v20,adc /v33i +- 5% adc_vccres 0x399 adc result for the (scaled) voltage on pin v cc 1 lsb=v cc *scale vcc,adc /v33i +- 5% adc_viores 0x39a adc result for the (scaled) voltage on v io 1 lsb=v io *scale vio,adc /v33i +- 5% table 63. voltage supervision registers back to table 8 register table adc_vbusp_mean msb lsb content v7 v6 v5 v4 v3 v2 v1 v0 hard reset value 0 0 0 0 0 0 0 0 soft reset value - (not reset) access r 1) r 1) r 1) r 1) r 1) r 1) r 1) r 1) table 64. mean value for v busp voltage the measurement values are scaled to limit them below the supply voltage (v33i) of the adc and analog to digi - tal converted. for scaling values look at chapter electrical charecteristics section monitoring functions . digital monitoring registers back to table 8 register table back to table 8 register table adc_vstres msb lsb content v7 v6 v5 v4 v3 v2 v1 v0 hard reset value 0 0 0 0 0 0 0 0 soft reset value - (not reset) access r 1) r 1) r 1) r 1) r 1) r 1) r 1) r 1) adc_v20res msb lsb content v7 v6 v5 v4 v3 v2 v1 v0 hard reset value 0 0 0 0 0 0 0 0 soft reset value - (not reset) access r 1) r 1) r 1) r 1) r 1) r 1) r 1) r 1) table 65. adc result for the (scaled) voltage on v st table 66. adc result for the (scaled) voltage on v 20 back to table 8 register table adc_vccres msb lsb content v7 v6 v5 v4 v3 v2 v1 v0 hard reset value 0 0 0 0 0 0 0 0 soft reset value - (not reset) access r 1) r 1) r 1) r 1) r 1) r 1) r 1) r 1) table 67. adc result for the (scaled) voltage on pin v cc elmos semiconductor ag data sheet qm-no.: 25ds0046e.03 production data - jan 15, 2015 elmos semiconductor ag reserves the right to change the detail specifcations as may be required to permit improvements in the design of its products. knx / eib transceiver e981.03
48/51 register name address description adc_tempres 0x39e adc result temperature scan register name address description aout_src 0x212 aout source select register aout_ctrl 0x211 aout control register aout_src value source 0x00 none; output is high impedance 0x01 temperature voltage 0x02 v busp / 8 or v busp / 12 depending on aout_ctrl register setting 0x03 bandgap voltage table 69. temperature supervision registers table 71. analog monitor register table 73. analog monitor multiplexer sources temperature supervision register the temperature supervision is necessary for protection in case of high power dissipation in failure cases, for ex - ample short circuit of supply outputs. for details read chapter 8.3 temperature supervision . analog monitor pin the pin aout is used to monitor several voltages. for details read chapter 5.5 aout . 1) access via uart service and spi possible. for write access read the remarks of every bit carefully. in case of hard or soft reset the register is reset to the hard reset value or soft reset value respectively. back to table 8 register table back to table 8 register table adc_tempres msb lsb content t7 t6 t5 t4 t3 t2 t1 t0 hard reset value 0 0 0 0 0 0 0 0 soft reset value - (not reset) access r 1) r 1) r 1) r 1) r 1) r 1) r 1) r 1) aout_src msb lsb content - - - - - - s1 s0 hard reset value 0 0 0 0 0 0 1 0 soft reset value - - - - - - 1 0 access r r r r r r r/w 1) r/w 1) table 70. adc result temperature scan table 72. source selector register for multiplexer on analog monitor pin back to table 8 register table adc_viores msb lsb content v7 v6 v5 v4 v3 v2 v1 v0 hard reset value 0 0 0 0 0 0 0 0 soft reset value - (not reset) access r 1) r 1) r 1) r 1) r 1) r 1) r 1) r 1) table 68. adc result for the (scaled) voltage on v io 1) access via uart service and spi possible. in case of hard reset the register is reset to the hard reset value. 1) access via uart service and spi possible. in case of hard reset the register is reset to the hard reset value. elmos semiconductor ag data sheet qm-no.: 25ds0046e.03 production data - jan 15, 2015 elmos semiconductor ag reserves the right to change the detail specifcations as may be required to permit improvements in the design of its products. knx / eib transceiver e981.03
49/51 aout_ctrl value source 0 v busp / 12 1 v busp / 8 table 75. analog busp voltage multiplexer 1) access via uart service and spi possible. for write access read the remarks of every bit carefully. in case of hard or soft reset the register is reset to the hard reset value or soft reset value respectively. in case of vio = 3.3 v and bus voltage divider selection of v busp / 12 pin voltage aout will not be higher than vio even if v busp / 12 is higher. back to table 8 register table aout_ctrl msb lsb content - - - - - - - div hard reset value 0 0 0 0 0 0 0 1 soft reset value - - - - - - - 1 access r r r r r r r r/w 1) table 74. bus voltage divider selection register elmos semiconductor ag data sheet qm-no.: 25ds0046e.03 production data - jan 15, 2015 elmos semiconductor ag reserves the right to change the detail specifcations as may be required to permit improvements in the design of its products. knx / eib transceiver e981.03
50/51 the e981.03 is available in a pb free, rohs compliant, qfn32l7 plastic package according to jedec mo-220 k, vari - ant vkkc-2. the package is classifed to moisture sensitivity level 3 (msl 3) according to jedec j-std-020d with a soldering peak temperature of (2605) c. p ackage o utline s pecification date : 05.01.2012 author: asto 32 lead quad flat non leaded package (qfn32l7) qm-no.: 08sp0677.04 package outline and dimensions are according jedec mo-220 k, variant vkkc-2 description symbol mm inch min typ max min typ max package height a 0.80 0.90 1.00 0.031 0.035 0.039 stand off a1 0.00 0 .02 0.05 0.000 0.00079 0.002 thickness of terminal leads, including lead finish a3 -- 0.20 ref -- -- 0.0079 ref -- width of terminal leads b 0.25 0.30 0.35 0.010 0.012 0.014 package length / width d / e -- 7.00 bsc -- -- 0.276 bsc -- length / width of exposed pad d2 / e2 5.50 5.65 5.80 0.217 0.223 0.229 lead pitch e -- 0.65 bsc -- -- 0.026 bsc -- length of terminal for soldering to substrate l 0.35 0.40 0.45 0.014 0.016 0.018 number of terminal positions n 32 32 note: the mm values are valid, the inch values contains rounding errors note 1: for assembler specific pin1 identification please see qm-document 08sp0363.xx (pin 1 specification) page 1 of 1 11 package information elmos semiconductor ag data sheet qm-no.: 25ds0046e.03 production data - jan 15, 2015 elmos semiconductor ag reserves the right to change the detail specifcations as may be required to permit improvements in the design of its products. knx / eib transceiver e981.03
51/51 warning ? life support applications policy elmos semiconductor ag is continually working to improve the quality and reliability of its products. neverthe- less, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vul- nerability to physical stress. it is the responsibility of the buyer, when utilizing elmos semiconductor ag products, to observe standards of safety, and to avoid situations in which malfunction or failure of an elmos semiconductor ag product could cause loss of human life, body injury or damage to property. in the development of your design, please ensure that elmos semiconductor ag products are used within speci? ed operating ranges as set forth in the most recent product speci? cations. general disclaimer information furnished by elmos semiconductor ag is believed to be accurate and reliable. however, no responsibil- ity is assumed by elmos semiconductor ag for its use, nor for any infringements of patents or other rights of third parties, which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of elmos semiconductor ag. elmos semiconductor ag reserves the right to make changes to this document or the products contained therein without prior notice, to improve performance, reliability, or manufacturability. application disclaimer circuit diagrams may contain components not manufactured by elmos semiconductor ag, which are included as means of illustrating typical applications. consequently, complete information suf? cient for construction purpos- es is not necessarily given. the information in the application examples has been carefully checked and is believed to be entirely reliable. however, no responsibility is assumed for inaccuracies. furthermore, such information does not convey to the purchaser of the semiconductor devices described any license under the patent rights of elmos semiconductor ag or others. contact information headquarters elmos semiconductor ag heinrich-hertz-str. 1 ? d-44227 dortmund (germany) ? : +492317549100 ? : sales-germany@elmos.com ? : www.elmos.com sales and application support of? ce north america elmos na. inc. 32255 northwestern highway ? suite 220 farmington hills mi 48334 (usa) ? : +12488653200 ? : sales-usa@elmos.com sales and application support of? ce china elmos semiconductor technology (shanghai) co., ltd. unit 16b, 16f zhao feng world trade building, no. 369 jiang su road, chang ning district, shanghai, pr china, 200050 ? : +86216210 0908 ? : sales-china@elmos.com sales and application support of? ce korea elmos korea b-1007, u-space 2, #670 daewangpangyo-ro, sampyoung-dong, bunddang-gu, sungnam-si kyounggi-do 463-400 korea ? : +82317141131 ? : sales-korea@elmos.com sales and application support of? ce japan elmos japan k.k. br shibaura n bldg. 7f 3-20-9 shibaura, minato-ku, tokyo 108-0023 japan ? : +81334517101 ? : sales-japan@elmos.com sales and application support of? ce singapore elmos semiconductor singapore pte ltd. 3a international business park #09-13 icon@ibp ? 609935 singapore ? : +65 6908 1261 ? : sales-singapore@elmos.com ? elmos semiconductor ag, 2014. reproduction, in part or whole, without the prior written consent of elmos semiconductor ag, is prohibited. elmos semiconductor ag data sheet qm-no.: 25ds0046e.03 production data - jan 15, 2015 knx / eib transceiver e981.03 elmos semiconductor ag reserves the right to change the detail specifcations as may be required to permit improvements in the design of its products.

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